Lines Matching +full:clkf +full:- +full:- +full:-
169 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
176 struct ci_ps *ps = rps->ps_priv; in ci_get_ps()
185 switch (rdev->pdev->device) { in ci_initialize_powertune_defaults()
193 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
199 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
203 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
207 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
217 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
221 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
223 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
224 pi->caps_cac = false; in ci_initialize_powertune_defaults()
225 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
226 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
227 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
228 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
230 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
231 pi->caps_cac = true; in ci_initialize_powertune_defaults()
232 if (rdev->family == CHIP_HAWAII) in ci_initialize_powertune_defaults()
233 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
235 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
236 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
237 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
243 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; in ci_convert_to_vid()
249 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
250 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
251 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
254 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
255 return -EINVAL; in ci_populate_bapm_vddc_vid_sidd()
256 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
257 return -EINVAL; in ci_populate_bapm_vddc_vid_sidd()
258 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
259 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
260 return -EINVAL; in ci_populate_bapm_vddc_vid_sidd()
262 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
263 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
264 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
265 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
266 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
268 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
269 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
278 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
281 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
282 return -EINVAL; in ci_populate_vddc_vid()
284 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
285 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
293 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
295 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
296 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
297 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
298 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
306 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
309 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
310 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
311 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
312 pt_defaults->tdc_vddc_throttle_release_limit_perc; in ci_populate_tdc_limit()
313 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
321 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
328 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
329 pi->sram_end); in ci_populate_dw8()
331 return -EINVAL; in ci_populate_dw8()
333 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
342 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
343 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
344 rdev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
345 rdev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
347 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
348 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
356 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
357 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
378 return -EINVAL; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
379 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
380 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
390 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
392 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; in ci_populate_bapm_vddc_base_leakage_sidd()
393 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; in ci_populate_bapm_vddc_base_leakage_sidd()
395 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
396 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
404 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
407 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
408 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
413 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
414 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
417 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
418 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
424 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
425 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
428 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
431 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); in ci_populate_bapm_parameters_in_dpm_table()
432 def1 = pt_defaults->bapmti_r; in ci_populate_bapm_parameters_in_dpm_table()
433 def2 = pt_defaults->bapmti_rc; in ci_populate_bapm_parameters_in_dpm_table()
438 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); in ci_populate_bapm_parameters_in_dpm_table()
439 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); in ci_populate_bapm_parameters_in_dpm_table()
455 if (pi->caps_power_containment) { in ci_populate_pm_base()
459 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
487 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
488 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
501 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
510 if (pi->caps_db_ramping) { in ci_do_enable_didt()
519 if (pi->caps_td_ramping) { in ci_do_enable_didt()
528 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
546 return -EINVAL; in ci_program_pt_config_registers()
548 while (config_regs->offset != 0xFFFFFFFF) { in ci_program_pt_config_registers()
549 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { in ci_program_pt_config_registers()
550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); in ci_program_pt_config_registers()
552 switch (config_regs->type) { in ci_program_pt_config_registers()
554 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers()
557 data = RREG32_DIDT(config_regs->offset); in ci_program_pt_config_registers()
560 data = RREG32(config_regs->offset << 2); in ci_program_pt_config_registers()
564 data &= ~config_regs->mask; in ci_program_pt_config_registers()
565 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); in ci_program_pt_config_registers()
568 switch (config_regs->type) { in ci_program_pt_config_registers()
570 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
573 WREG32_DIDT(config_regs->offset, data); in ci_program_pt_config_registers()
576 WREG32(config_regs->offset << 2, data); in ci_program_pt_config_registers()
591 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
592 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
618 pi->power_containment_features = 0; in ci_enable_power_containment()
619 if (pi->caps_power_containment) { in ci_enable_power_containment()
620 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
623 ret = -EINVAL; in ci_enable_power_containment()
625 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
628 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
631 ret = -EINVAL; in ci_enable_power_containment()
633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
636 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
639 ret = -EINVAL; in ci_enable_power_containment()
642 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
644 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); in ci_enable_power_containment()
646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
653 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
654 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
657 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
662 pi->power_containment_features = 0; in ci_enable_power_containment()
675 if (pi->caps_cac) { in ci_enable_smc_cac()
679 ret = -EINVAL; in ci_enable_smc_cac()
680 pi->cac_enabled = false; in ci_enable_smc_cac()
682 pi->cac_enabled = true; in ci_enable_smc_cac()
684 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
686 pi->cac_enabled = false; in ci_enable_smc_cac()
699 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
709 return -EINVAL; in ci_enable_thermal_based_sclk_dpm()
716 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
722 if (pi->caps_power_containment) { in ci_power_control_set_level()
724 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
726 (s32)cac_tdp_table->configurable_tdp) / 100; in ci_power_control_set_level()
738 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
741 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
750 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
775 if (rps->vce_active) { in ci_apply_state_adjust_rules()
776 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
777 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
779 rps->evclk = 0; in ci_apply_state_adjust_rules()
780 rps->ecclk = 0; in ci_apply_state_adjust_rules()
783 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
789 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) in ci_apply_state_adjust_rules()
790 pi->battery_state = true; in ci_apply_state_adjust_rules()
792 pi->battery_state = false; in ci_apply_state_adjust_rules()
794 if (rdev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
795 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
797 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
799 if (rdev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
800 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()
801 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()
802 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()
803 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
804 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
811 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
812 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
814 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
815 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
818 if (rps->vce_active) { in ci_apply_state_adjust_rules()
819 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
820 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
821 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
822 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
825 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
826 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()
828 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) in ci_apply_state_adjust_rules()
829 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
832 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) in ci_apply_state_adjust_rules()
833 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; in ci_apply_state_adjust_rules()
835 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) in ci_apply_state_adjust_rules()
836 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
852 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in ci_thermal_set_temperature_range()
853 return -EINVAL; in ci_thermal_set_temperature_range()
870 rdev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
871 rdev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
885 rdev->irq.dpm_thermal = false; in ci_thermal_enable_alert()
889 return -EINVAL; in ci_thermal_enable_alert()
894 rdev->irq.dpm_thermal = true; in ci_thermal_enable_alert()
898 return -EINVAL; in ci_thermal_enable_alert()
910 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
912 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
914 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
915 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
938 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
939 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
946 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
950 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
954 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
955 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
957 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
958 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
963 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
964 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
965 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
972 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
982 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
991 pi->fan_table_start, in ci_thermal_setup_fan_table()
994 pi->sram_end); in ci_thermal_setup_fan_table()
998 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1009 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1014 return -EINVAL; in ci_fan_ctrl_start_smc_fan_control()
1017 rdev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1019 return -EINVAL; in ci_fan_ctrl_start_smc_fan_control()
1025 return -EINVAL; in ci_fan_ctrl_start_smc_fan_control()
1028 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1039 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1042 return -EINVAL; in ci_fan_ctrl_stop_smc_fan_control()
1051 if (rdev->pm.no_fan) in ci_fan_ctrl_get_fan_speed_percent()
1052 return -ENOENT; in ci_fan_ctrl_get_fan_speed_percent()
1058 return -EINVAL; in ci_fan_ctrl_get_fan_speed_percent()
1078 if (rdev->pm.no_fan) in ci_fan_ctrl_set_fan_speed_percent()
1079 return -ENOENT; in ci_fan_ctrl_set_fan_speed_percent()
1081 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1082 return -EINVAL; in ci_fan_ctrl_set_fan_speed_percent()
1085 return -EINVAL; in ci_fan_ctrl_set_fan_speed_percent()
1090 return -EINVAL; in ci_fan_ctrl_set_fan_speed_percent()
1106 /* stop auto-manage */ in ci_fan_ctrl_set_mode()
1107 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1111 /* restart auto-manage */ in ci_fan_ctrl_set_mode()
1112 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1124 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1138 if (rdev->pm.no_fan)
1139 return -ENOENT;
1141 if (rdev->pm.fan_pulses_per_revolution == 0)
1142 return -ENOENT;
1146 return -ENOENT;
1159 if (rdev->pm.no_fan)
1160 return -ENOENT;
1162 if (rdev->pm.fan_pulses_per_revolution == 0)
1163 return -ENOENT;
1165 if ((speed < rdev->pm.fan_min_rpm) ||
1166 (speed > rdev->pm.fan_max_rpm))
1167 return -EINVAL;
1169 if (rdev->pm.dpm.fan.ucode_fan_control)
1188 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1190 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1194 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1196 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1202 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1212 if (rdev->pm.fan_pulses_per_revolution) { in ci_thermal_initialize()
1214 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution - 1); in ci_thermal_initialize()
1234 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1246 if (!rdev->pm.no_fan) in ci_thermal_stop_thermal_controller()
1257 pi->soft_regs_start + reg_offset,
1258 value, pi->sram_end);
1268 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1269 value, pi->sram_end); in ci_write_smc_soft_register()
1275 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1277 if (pi->caps_fps) { in ci_init_fps_limits()
1281 table->FpsHighT = cpu_to_be16(tmp); in ci_init_fps_limits()
1284 table->FpsLowT = cpu_to_be16(tmp); in ci_init_fps_limits()
1294 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1295 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1298 pi->dpm_table_start + in ci_update_sclk_t()
1301 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1315 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1316 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1318 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1324 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1325 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1326 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1336 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1337 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1338 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1341 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1342 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1343 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1375 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1394 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1395 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1396 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1399 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1400 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1401 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1408 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1417 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1420 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1421 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1424 return -EINVAL; in ci_unfreeze_sclk_mclk_dpm()
1427 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1428 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1431 return -EINVAL; in ci_unfreeze_sclk_mclk_dpm()
1434 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1444 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1447 return -EINVAL; in ci_enable_sclk_mclk_dpm()
1450 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1453 return -EINVAL; in ci_enable_sclk_mclk_dpm()
1468 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1471 return -EINVAL; in ci_enable_sclk_mclk_dpm()
1474 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1477 return -EINVAL; in ci_enable_sclk_mclk_dpm()
1505 return -EINVAL; in ci_start_dpm()
1511 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1514 return -EINVAL; in ci_start_dpm()
1525 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1528 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1529 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1532 return -EINVAL; in ci_freeze_sclk_mclk_dpm()
1535 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1536 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1539 return -EINVAL; in ci_freeze_sclk_mclk_dpm()
1560 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1563 return -EINVAL; in ci_stop_dpm()
1572 return -EINVAL; in ci_stop_dpm()
1594 rdev->pm.dpm.dyn_state.cac_tdp_table;
1598 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1600 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1604 if (pi->caps_automatic_dc_transition) {
1625 for (i = 0; i < rdev->usec_timeout; i++) { in ci_send_msg_to_smc()
1660 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1664 return -EINVAL; in ci_dpm_force_state_sclk()
1674 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1678 return -EINVAL; in ci_dpm_force_state_mclk()
1688 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1692 return -EINVAL; in ci_dpm_force_state_pcie()
1702 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1706 return -EINVAL; in ci_set_power_limit()
1718 return -EINVAL; in ci_set_overdrive_target_tdp()
1762 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_start_smc()
1783 &tmp, pi->sram_end); in ci_process_firmware_header()
1787 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1792 &tmp, pi->sram_end); in ci_process_firmware_header()
1796 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1801 &tmp, pi->sram_end); in ci_process_firmware_header()
1805 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1810 &tmp, pi->sram_end); in ci_process_firmware_header()
1814 pi->fan_table_start = tmp; in ci_process_firmware_header()
1819 &tmp, pi->sram_end); in ci_process_firmware_header()
1823 pi->arb_table_start = tmp; in ci_process_firmware_header()
1832 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1834 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1836 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1838 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1840 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1842 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1844 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1845 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1846 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1847 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1848 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1849 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1850 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1851 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1852 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1859 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1902 for (i = 0; i < rdev->usec_timeout; i++) {
1917 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; in ci_notify_smc_display_change()
1926 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1928 return -EINVAL; in ci_enable_ds_master_switch()
1931 return -EINVAL; in ci_enable_ds_master_switch()
1934 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1936 return -EINVAL; in ci_enable_ds_master_switch()
1948 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap()
1953 if (rdev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
1965 frame_time_in_us - 200 - vblank_time; in ci_program_display_gap()
1970 …ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - … in ci_program_display_gap()
1973 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
1983 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2056 for (i = 0; i < rdev->usec_timeout; i++) { in ci_upload_firmware()
2065 return ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2076 return -EINVAL; in ci_get_svi2_voltage_table()
2078 voltage_table->mask_low = 0; in ci_get_svi2_voltage_table()
2079 voltage_table->phase_delay = 0; in ci_get_svi2_voltage_table()
2081 voltage_table->count = voltage_dependency_table->count; in ci_get_svi2_voltage_table()
2082 for (i = 0; i < voltage_table->count; i++) { in ci_get_svi2_voltage_table()
2083 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; in ci_get_svi2_voltage_table()
2084 voltage_table->entries[i].smio_low = 0; in ci_get_svi2_voltage_table()
2095 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2098 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2101 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2103 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2104 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2109 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2111 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2113 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2116 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2119 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2121 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2122 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2127 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2129 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2131 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2134 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2137 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2139 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2140 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2145 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2147 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2159 &smc_voltage_table->StdVoltageHiSidd, in ci_populate_smc_voltage_table()
2160 &smc_voltage_table->StdVoltageLoSidd); in ci_populate_smc_voltage_table()
2163 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; in ci_populate_smc_voltage_table()
2164 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; in ci_populate_smc_voltage_table()
2167 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); in ci_populate_smc_voltage_table()
2168 smc_voltage_table->StdVoltageHiSidd = in ci_populate_smc_voltage_table()
2169 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); in ci_populate_smc_voltage_table()
2170 smc_voltage_table->StdVoltageLoSidd = in ci_populate_smc_voltage_table()
2171 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); in ci_populate_smc_voltage_table()
2180 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2181 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
2183 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2184 &table->VddcLevel[count]); in ci_populate_smc_vddc_table()
2186 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2187 table->VddcLevel[count].Smio |= in ci_populate_smc_vddc_table()
2188 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2190 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
2192 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); in ci_populate_smc_vddc_table()
2203 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2204 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
2206 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2207 &table->VddciLevel[count]); in ci_populate_smc_vddci_table()
2209 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2210 table->VddciLevel[count].Smio |= in ci_populate_smc_vddci_table()
2211 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2213 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
2215 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); in ci_populate_smc_vddci_table()
2226 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2227 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
2229 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2230 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
2232 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2233 table->MvddLevel[count].Smio |= in ci_populate_smc_mvdd_table()
2234 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2236 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
2238 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
2269 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2270 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2271 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2272 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2277 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2278 return -EINVAL; in ci_populate_mvdd_value()
2281 return -EINVAL; in ci_populate_mvdd_value()
2290 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2291 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2293 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2294 return -EINVAL; in ci_get_std_voltage_value_sidd()
2296 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2297 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2298 if (voltage_table->value == in ci_get_std_voltage_value_sidd()
2299 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2301 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2304 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2306 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2308 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2314 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2315 if (voltage_table->value <= in ci_get_std_voltage_value_sidd()
2316 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2318 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2321 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2323 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2325 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2344 for (i = 0; i < limits->count; i++) { in ci_populate_phase_value_based_on_sclk()
2345 if (sclk < limits->entries[i].sclk) { in ci_populate_phase_value_based_on_sclk()
2361 for (i = 0; i < limits->count; i++) { in ci_populate_phase_value_based_on_mclk()
2362 if (mclk < limits->entries[i].mclk) { in ci_populate_phase_value_based_on_mclk()
2375 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2376 &tmp, pi->sram_end); in ci_init_arb_table_index()
2383 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2384 tmp, pi->sram_end); in ci_init_arb_table_index()
2393 if (allowed_clock_voltage_table->count == 0) in ci_get_dependency_volt_by_clk()
2394 return -EINVAL; in ci_get_dependency_volt_by_clk()
2396 for (i = 0; i < allowed_clock_voltage_table->count; i++) { in ci_get_dependency_volt_by_clk()
2397 if (allowed_clock_voltage_table->entries[i].clk >= clock) { in ci_get_dependency_volt_by_clk()
2398 *voltage = allowed_clock_voltage_table->entries[i].v; in ci_get_dependency_volt_by_clk()
2403 *voltage = allowed_clock_voltage_table->entries[i-1].v; in ci_get_dependency_volt_by_clk()
2419 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { in ci_get_sleep_divider_id_from_clock()
2436 0 : -EINVAL; in ci_reset_to_default()
2463 ((rdev->pdev->device == 0x67B0) || in ci_register_patching_mc_arb()
2464 (rdev->pdev->device == 0x67B1))) { in ci_register_patching_mc_arb()
2466 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2470 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
2495 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); in ci_populate_memory_timing_parameters()
2496 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); in ci_populate_memory_timing_parameters()
2497 arb_regs->McArbBurstTime = (u8)burst_time; in ci_populate_memory_timing_parameters()
2511 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2512 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2514 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2515 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2524 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2527 pi->sram_end); in ci_do_program_memory_timing_parameters()
2536 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2549 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2550 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2551 boot_state->performance_levels[0].sclk) { in ci_populate_smc_initial_state()
2552 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2557 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2558 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2559 boot_state->performance_levels[0].mclk) { in ci_populate_smc_initial_state()
2560 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2571 for (i = dpm_table->count; i > 0; i--) { in ci_get_dpm_level_enable_mask_value()
2573 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2586 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2589 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
2590 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2591 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2592 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2593 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
2594 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2595 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2596 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2600 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2601 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in ci_populate_smc_link_level()
2609 int ret = -EINVAL; in ci_populate_smc_uvd_level()
2611 table->UvdLevelCount = in ci_populate_smc_uvd_level()
2612 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2614 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2615 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2616 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2617 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2618 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2619 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2620 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2621 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2625 table->UvdLevel[count].VclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2629 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2633 table->UvdLevel[count].DclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2637 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2639 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2640 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
2641 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
2652 int ret = -EINVAL; in ci_populate_smc_vce_level()
2654 table->VceLevelCount = in ci_populate_smc_vce_level()
2655 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2657 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2658 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2659 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2660 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2661 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2662 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2666 table->VceLevel[count].Frequency, false, ÷rs); in ci_populate_smc_vce_level()
2670 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2672 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2673 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
2685 int ret = -EINVAL; in ci_populate_smc_acp_level()
2687 table->AcpLevelCount = (u8) in ci_populate_smc_acp_level()
2688 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2690 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2691 table->AcpLevel[count].Frequency = in ci_populate_smc_acp_level()
2692 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2693 table->AcpLevel[count].MinVoltage = in ci_populate_smc_acp_level()
2694 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2695 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
2699 table->AcpLevel[count].Frequency, false, ÷rs); in ci_populate_smc_acp_level()
2703 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2705 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
2706 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
2717 int ret = -EINVAL; in ci_populate_smc_samu_level()
2719 table->SamuLevelCount = in ci_populate_smc_samu_level()
2720 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2722 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2723 table->SamuLevel[count].Frequency = in ci_populate_smc_samu_level()
2724 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2725 table->SamuLevel[count].MinVoltage = in ci_populate_smc_samu_level()
2726 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2727 table->SamuLevel[count].MinPhases = 1; in ci_populate_smc_samu_level()
2731 table->SamuLevel[count].Frequency, false, ÷rs); in ci_populate_smc_samu_level()
2735 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2737 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); in ci_populate_smc_samu_level()
2738 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); in ci_populate_smc_samu_level()
2751 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2752 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2753 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2754 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2755 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2756 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2757 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2758 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2759 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2771 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | in ci_calculate_mclk_params()
2777 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2783 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2787 u32 reference_clock = rdev->clock.mpll.reference_freq; in ci_calculate_mclk_params()
2817 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
2818 mclk->MpllFuncCntl = mpll_func_cntl; in ci_calculate_mclk_params()
2819 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in ci_calculate_mclk_params()
2820 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in ci_calculate_mclk_params()
2821 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in ci_calculate_mclk_params()
2822 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in ci_calculate_mclk_params()
2823 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2824 mclk->DllCntl = dll_cntl; in ci_calculate_mclk_params()
2825 mclk->MpllSs1 = mpll_ss1; in ci_calculate_mclk_params()
2826 mclk->MpllSs2 = mpll_ss2; in ci_calculate_mclk_params()
2839 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2841 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2842 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
2847 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2849 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
2850 memory_clock, &memory_level->MinVddci); in ci_populate_single_memory_level()
2855 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2857 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2858 memory_clock, &memory_level->MinMvdd); in ci_populate_single_memory_level()
2863 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()
2865 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2867 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
2869 &memory_level->MinVddcPhases); in ci_populate_single_memory_level()
2871 memory_level->EnabledForThrottle = 1; in ci_populate_single_memory_level()
2872 memory_level->UpH = 0; in ci_populate_single_memory_level()
2873 memory_level->DownH = 100; in ci_populate_single_memory_level()
2874 memory_level->VoltageDownH = 0; in ci_populate_single_memory_level()
2875 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2877 memory_level->StutterEnable = false; in ci_populate_single_memory_level()
2878 memory_level->StrobeEnable = false; in ci_populate_single_memory_level()
2879 memory_level->EdcReadEnable = false; in ci_populate_single_memory_level()
2880 memory_level->EdcWriteEnable = false; in ci_populate_single_memory_level()
2881 memory_level->RttEnable = false; in ci_populate_single_memory_level()
2883 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_single_memory_level()
2885 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2886 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2887 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2889 (rdev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
2890 memory_level->StutterEnable = true; in ci_populate_single_memory_level()
2892 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2893 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2894 memory_level->StrobeEnable = 1; in ci_populate_single_memory_level()
2896 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2897 memory_level->StrobeRatio = in ci_populate_single_memory_level()
2898 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); in ci_populate_single_memory_level()
2899 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2900 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2901 memory_level->EdcReadEnable = true; in ci_populate_single_memory_level()
2903 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2904 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2905 memory_level->EdcWriteEnable = true; in ci_populate_single_memory_level()
2907 if (memory_level->StrobeEnable) { in ci_populate_single_memory_level()
2914 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2917 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); in ci_populate_single_memory_level()
2921 …ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s… in ci_populate_single_memory_level()
2925 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); in ci_populate_single_memory_level()
2926 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); in ci_populate_single_memory_level()
2927 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); in ci_populate_single_memory_level()
2928 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); in ci_populate_single_memory_level()
2930 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); in ci_populate_single_memory_level()
2931 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); in ci_populate_single_memory_level()
2932 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); in ci_populate_single_memory_level()
2933 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); in ci_populate_single_memory_level()
2934 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); in ci_populate_single_memory_level()
2935 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); in ci_populate_single_memory_level()
2936 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); in ci_populate_single_memory_level()
2937 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); in ci_populate_single_memory_level()
2938 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); in ci_populate_single_memory_level()
2939 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); in ci_populate_single_memory_level()
2940 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); in ci_populate_single_memory_level()
2951 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2952 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2953 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2954 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2957 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
2959 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2960 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2962 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2964 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2966 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
2970 table->ACPILevel.SclkFrequency, false, ÷rs); in ci_populate_smc_acpi_level()
2974 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
2975 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
2976 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
2984 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
2985 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
2986 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
2987 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
2988 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
2989 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
2990 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
2991 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
2993 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
2994 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
2995 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
2996 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
2997 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
2998 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
2999 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
3000 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
3001 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
3002 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
3003 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
3005 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
3006 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
3008 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3009 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3010 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3011 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3013 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3014 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3018 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
3020 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
3028 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); in ci_populate_smc_acpi_level()
3029 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); in ci_populate_smc_acpi_level()
3030 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
3031 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3032 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
3033 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3034 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
3035 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3036 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
3037 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3038 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
3039 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3040 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3041 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3043 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
3044 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
3045 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
3046 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
3047 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
3048 table->MemoryACPILevel.ActivityLevel = in ci_populate_smc_acpi_level()
3049 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3051 table->MemoryACPILevel.StutterEnable = false; in ci_populate_smc_acpi_level()
3052 table->MemoryACPILevel.StrobeEnable = false; in ci_populate_smc_acpi_level()
3053 table->MemoryACPILevel.EdcReadEnable = false; in ci_populate_smc_acpi_level()
3054 table->MemoryACPILevel.EdcWriteEnable = false; in ci_populate_smc_acpi_level()
3055 table->MemoryACPILevel.RttEnable = false; in ci_populate_smc_acpi_level()
3064 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3066 if (ulv->supported) { in ci_enable_ulv()
3069 0 : -EINVAL; in ci_enable_ulv()
3072 0 : -EINVAL; in ci_enable_ulv()
3082 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3084 state->CcPwrDynRm = 0; in ci_populate_ulv_level()
3085 state->CcPwrDynRm1 = 0; in ci_populate_ulv_level()
3088 pi->ulv.supported = false; in ci_populate_ulv_level()
3092 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3093 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3094 state->VddcOffset = 0; in ci_populate_ulv_level()
3096 state->VddcOffset = in ci_populate_ulv_level()
3097 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3099 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3100 state->VddcOffsetVid = 0; in ci_populate_ulv_level()
3102 state->VddcOffsetVid = (u8) in ci_populate_ulv_level()
3103 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3106 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3108 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); in ci_populate_ulv_level()
3109 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); in ci_populate_ulv_level()
3110 state->VddcOffset = cpu_to_be16(state->VddcOffset); in ci_populate_ulv_level()
3121 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3122 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3123 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3124 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3125 u32 reference_clock = rdev->clock.spll.reference_freq; in ci_calculate_sclk_params()
3143 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3161 sclk->SclkFrequency = engine_clock; in ci_calculate_sclk_params()
3162 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; in ci_calculate_sclk_params()
3163 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; in ci_calculate_sclk_params()
3164 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3165 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3166 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
3184 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3185 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
3189 graphic_level->SclkFrequency = engine_clock; in ci_populate_single_graphic_level()
3191 graphic_level->Flags = 0; in ci_populate_single_graphic_level()
3192 graphic_level->MinVddcPhases = 1; in ci_populate_single_graphic_level()
3194 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3196 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3198 &graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()
3200 graphic_level->ActivityLevel = sclk_activity_level_t; in ci_populate_single_graphic_level()
3202 graphic_level->CcPwrDynRm = 0; in ci_populate_single_graphic_level()
3203 graphic_level->CcPwrDynRm1 = 0; in ci_populate_single_graphic_level()
3204 graphic_level->EnabledForThrottle = 1; in ci_populate_single_graphic_level()
3205 graphic_level->UpH = 0; in ci_populate_single_graphic_level()
3206 graphic_level->DownH = 0; in ci_populate_single_graphic_level()
3207 graphic_level->VoltageDownH = 0; in ci_populate_single_graphic_level()
3208 graphic_level->PowerThrottle = 0; in ci_populate_single_graphic_level()
3210 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3211 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, in ci_populate_single_graphic_level()
3215 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_single_graphic_level()
3217 graphic_level->Flags = cpu_to_be32(graphic_level->Flags); in ci_populate_single_graphic_level()
3218 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); in ci_populate_single_graphic_level()
3219 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()
3220 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); in ci_populate_single_graphic_level()
3221 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); in ci_populate_single_graphic_level()
3222 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); in ci_populate_single_graphic_level()
3223 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); in ci_populate_single_graphic_level()
3224 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); in ci_populate_single_graphic_level()
3225 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); in ci_populate_single_graphic_level()
3226 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); in ci_populate_single_graphic_level()
3227 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); in ci_populate_single_graphic_level()
3235 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3236 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3240 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3245 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3247 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3248 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3249 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3253 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3254 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3255 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3258 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3260 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3261 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3262 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3266 pi->sram_end); in ci_populate_all_graphic_levels()
3282 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3283 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3287 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3292 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3293 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3294 return -EINVAL; in ci_populate_all_memory_levels()
3296 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3297 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3302 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3304 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3305 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) { in ci_populate_all_memory_levels()
3306 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3307 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3308 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3309 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3312 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3314 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3315 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3316 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3318 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3323 pi->sram_end); in ci_populate_all_memory_levels()
3336 dpm_table->count = count; in ci_reset_single_dpm_table()
3338 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3344 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
3345 dpm_table->dpm_levels[index].param1 = pcie_lanes; in ci_setup_pcie_table_entry()
3346 dpm_table->dpm_levels[index].enabled = true; in ci_setup_pcie_table_entry()
3353 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3354 return -EINVAL; in ci_setup_default_pcie_tables()
3356 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3357 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3358 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3359 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3360 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3361 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3365 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3368 if (rdev->family == CHIP_BONAIRE) in ci_setup_default_pcie_tables()
3369 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3370 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3371 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3374 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3375 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3376 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3377 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3378 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3379 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3380 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3381 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3382 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3383 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3384 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3385 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3386 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3387 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3388 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3389 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3390 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3392 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3401 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3403 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3405 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3409 return -EINVAL; in ci_setup_default_dpm_tables()
3410 if (allowed_sclk_vddc_table->count < 1) in ci_setup_default_dpm_tables()
3411 return -EINVAL; in ci_setup_default_dpm_tables()
3413 return -EINVAL; in ci_setup_default_dpm_tables()
3414 if (allowed_mclk_table->count < 1) in ci_setup_default_dpm_tables()
3415 return -EINVAL; in ci_setup_default_dpm_tables()
3417 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3420 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3423 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3426 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3429 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3432 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3435 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3436 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()
3438 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3439 allowed_sclk_vddc_table->entries[i].clk)) { in ci_setup_default_dpm_tables()
3440 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3441 allowed_sclk_vddc_table->entries[i].clk; in ci_setup_default_dpm_tables()
3442 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3444 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3448 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3449 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()
3451 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3452 allowed_mclk_table->entries[i].clk)) { in ci_setup_default_dpm_tables()
3453 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3454 allowed_mclk_table->entries[i].clk; in ci_setup_default_dpm_tables()
3455 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3457 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3461 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()
3462 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3463 allowed_sclk_vddc_table->entries[i].v; in ci_setup_default_dpm_tables()
3464 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3465 std_voltage_table->entries[i].leakage; in ci_setup_default_dpm_tables()
3466 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3468 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3470 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3472 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()
3473 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3474 allowed_mclk_table->entries[i].v; in ci_setup_default_dpm_tables()
3475 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3477 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3480 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3482 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()
3483 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3484 allowed_mclk_table->entries[i].v; in ci_setup_default_dpm_tables()
3485 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3487 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3499 int ret = -EINVAL; in ci_find_boot_level()
3501 for (i = 0; i < table->count; i++) { in ci_find_boot_level()
3502 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3514 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3515 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in ci_init_smc_table()
3516 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3523 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3528 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3529 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
3531 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3532 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
3534 if (pi->mem_gddr5) in ci_init_smc_table()
3535 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
3537 if (ulv->supported) { in ci_init_smc_table()
3538 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3541 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in ci_init_smc_table()
3578 table->UvdBootLevel = 0; in ci_init_smc_table()
3579 table->VceBootLevel = 0; in ci_init_smc_table()
3580 table->AcpBootLevel = 0; in ci_init_smc_table()
3581 table->SamuBootLevel = 0; in ci_init_smc_table()
3582 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3583 table->MemoryBootLevel = 0; in ci_init_smc_table()
3585 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3586 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3587 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3589 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3590 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3591 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3593 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3594 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3595 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3603 table->UVDInterval = 1; in ci_init_smc_table()
3604 table->VCEInterval = 1; in ci_init_smc_table()
3605 table->ACPInterval = 1; in ci_init_smc_table()
3606 table->SAMUInterval = 1; in ci_init_smc_table()
3607 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
3608 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
3609 table->GraphicsInterval = 1; in ci_init_smc_table()
3610 table->VoltageInterval = 1; in ci_init_smc_table()
3611 table->ThermalInterval = 1; in ci_init_smc_table()
3612 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3614 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3616 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
3617 table->MemoryInterval = 1; in ci_init_smc_table()
3618 table->VoltageResponseTime = 0; in ci_init_smc_table()
3619 table->VddcVddciDelta = 4000; in ci_init_smc_table()
3620 table->PhaseResponseTime = 0; in ci_init_smc_table()
3621 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
3622 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3623 table->PCIeGenInterval = 1; in ci_init_smc_table()
3624 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3625 table->SVI2Enable = 1; in ci_init_smc_table()
3627 table->SVI2Enable = 0; in ci_init_smc_table()
3629 table->ThermGpio = 17; in ci_init_smc_table()
3630 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3632 table->SystemFlags = cpu_to_be32(table->SystemFlags); in ci_init_smc_table()
3633 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); in ci_init_smc_table()
3634 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); in ci_init_smc_table()
3635 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); in ci_init_smc_table()
3636 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); in ci_init_smc_table()
3637 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); in ci_init_smc_table()
3638 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); in ci_init_smc_table()
3639 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); in ci_init_smc_table()
3640 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); in ci_init_smc_table()
3641 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); in ci_init_smc_table()
3642 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); in ci_init_smc_table()
3643 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
3644 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
3645 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
3648 pi->dpm_table_start + in ci_init_smc_table()
3650 (u8 *)&table->SystemFlags, in ci_init_smc_table()
3651 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), in ci_init_smc_table()
3652 pi->sram_end); in ci_init_smc_table()
3665 for (i = 0; i < dpm_table->count; i++) { in ci_trim_single_dpm_states()
3666 if ((dpm_table->dpm_levels[i].value < low_limit) || in ci_trim_single_dpm_states()
3667 (dpm_table->dpm_levels[i].value > high_limit)) in ci_trim_single_dpm_states()
3668 dpm_table->dpm_levels[i].enabled = false; in ci_trim_single_dpm_states()
3670 dpm_table->dpm_levels[i].enabled = true; in ci_trim_single_dpm_states()
3679 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3682 for (i = 0; i < pcie_table->count; i++) { in ci_trim_pcie_dpm_states()
3683 if ((pcie_table->dpm_levels[i].value < speed_low) || in ci_trim_pcie_dpm_states()
3684 (pcie_table->dpm_levels[i].param1 < lanes_low) || in ci_trim_pcie_dpm_states()
3685 (pcie_table->dpm_levels[i].value > speed_high) || in ci_trim_pcie_dpm_states()
3686 (pcie_table->dpm_levels[i].param1 > lanes_high)) in ci_trim_pcie_dpm_states()
3687 pcie_table->dpm_levels[i].enabled = false; in ci_trim_pcie_dpm_states()
3689 pcie_table->dpm_levels[i].enabled = true; in ci_trim_pcie_dpm_states()
3692 for (i = 0; i < pcie_table->count; i++) { in ci_trim_pcie_dpm_states()
3693 if (pcie_table->dpm_levels[i].enabled) { in ci_trim_pcie_dpm_states()
3694 for (j = i + 1; j < pcie_table->count; j++) { in ci_trim_pcie_dpm_states()
3695 if (pcie_table->dpm_levels[j].enabled) { in ci_trim_pcie_dpm_states()
3696 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && in ci_trim_pcie_dpm_states()
3697 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) in ci_trim_pcie_dpm_states()
3698 pcie_table->dpm_levels[j].enabled = false; in ci_trim_pcie_dpm_states()
3712 if (state->performance_level_count < 1) in ci_trim_dpm_states()
3713 return -EINVAL; in ci_trim_dpm_states()
3715 if (state->performance_level_count == 1) in ci_trim_dpm_states()
3721 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3722 state->performance_levels[0].sclk, in ci_trim_dpm_states()
3723 state->performance_levels[high_limit_count].sclk); in ci_trim_dpm_states()
3726 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3727 state->performance_levels[0].mclk, in ci_trim_dpm_states()
3728 state->performance_levels[high_limit_count].mclk); in ci_trim_dpm_states()
3731 state->performance_levels[0].pcie_gen, in ci_trim_dpm_states()
3732 state->performance_levels[0].pcie_lane, in ci_trim_dpm_states()
3733 state->performance_levels[high_limit_count].pcie_gen, in ci_trim_dpm_states()
3734 state->performance_levels[high_limit_count].pcie_lane); in ci_trim_dpm_states()
3742 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3744 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3749 return -EINVAL; in ci_apply_disp_minimum_voltage_request()
3750 if (!disp_voltage_table->count) in ci_apply_disp_minimum_voltage_request()
3751 return -EINVAL; in ci_apply_disp_minimum_voltage_request()
3753 for (i = 0; i < disp_voltage_table->count; i++) { in ci_apply_disp_minimum_voltage_request()
3754 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) in ci_apply_disp_minimum_voltage_request()
3755 requested_voltage = disp_voltage_table->entries[i].v; in ci_apply_disp_minimum_voltage_request()
3758 for (i = 0; i < vddc_table->count; i++) { in ci_apply_disp_minimum_voltage_request()
3759 if (requested_voltage <= vddc_table->entries[i].v) { in ci_apply_disp_minimum_voltage_request()
3760 requested_voltage = vddc_table->entries[i].v; in ci_apply_disp_minimum_voltage_request()
3764 0 : -EINVAL; in ci_apply_disp_minimum_voltage_request()
3768 return -EINVAL; in ci_apply_disp_minimum_voltage_request()
3778 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3779 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3782 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3784 return -EINVAL; in ci_upload_dpm_level_enable_mask()
3788 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3789 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3792 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3794 return -EINVAL; in ci_upload_dpm_level_enable_mask()
3798 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3799 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3802 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3804 return -EINVAL; in ci_upload_dpm_level_enable_mask()
3816 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3817 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()
3818 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3819 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()
3822 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3824 for (i = 0; i < sclk_table->count; i++) { in ci_find_dpm_states_clocks_in_dpm_table()
3825 if (sclk == sclk_table->dpm_levels[i].value) in ci_find_dpm_states_clocks_in_dpm_table()
3829 if (i >= sclk_table->count) { in ci_find_dpm_states_clocks_in_dpm_table()
3830 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3837 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3840 for (i = 0; i < mclk_table->count; i++) { in ci_find_dpm_states_clocks_in_dpm_table()
3841 if (mclk == mclk_table->dpm_levels[i].value) in ci_find_dpm_states_clocks_in_dpm_table()
3845 if (i >= mclk_table->count) in ci_find_dpm_states_clocks_in_dpm_table()
3846 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3848 if (rdev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
3849 rdev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
3850 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3858 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3859 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3860 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3863 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3866 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3867 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3869 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3870 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3872 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3878 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3893 if (rdev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
3894 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
3896 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
3899 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3901 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3902 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
3903 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3905 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3912 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3914 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3915 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3916 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3919 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3922 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3923 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3924 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3927 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3933 0 : -EINVAL; in ci_enable_uvd_dpm()
3942 if (rdev->pm.dpm.ac_power) in ci_enable_vce_dpm()
3943 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
3945 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
3948 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3949 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3950 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
3951 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3953 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3960 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
3965 0 : -EINVAL; in ci_enable_vce_dpm()
3975 if (rdev->pm.dpm.ac_power)
3976 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3978 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3981 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3982 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3983 … if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3984 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3986 if (!pi->caps_samu_dpm)
3993 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3997 0 : -EINVAL;
4006 if (rdev->pm.dpm.ac_power)
4007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4009 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4012 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4013 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4014 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4015 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4017 if (!pi->caps_acp_dpm)
4024 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4029 0 : -EINVAL;
4039 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4040 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4041 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4043 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4044 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4048 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4060 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4062 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
4063 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4067 return table->count - 1; in ci_get_vce_boot_level()
4078 if (radeon_current_state->evclk != radeon_new_state->evclk) { in ci_update_vce_dpm()
4079 if (radeon_new_state->evclk) { in ci_update_vce_dpm()
4083 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4086 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4112 pi->smc_state_table.AcpBootLevel = 0;
4116 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4134 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4135 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4136 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4137 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4138 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4139 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4140 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4141 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4142 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4144 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4145 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4170 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4171 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4173 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4180 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4189 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4190 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4192 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4199 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4208 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4209 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4211 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4218 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4228 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4229 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4231 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4235 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4243 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4244 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4246 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4250 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4258 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4259 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4261 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4265 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4274 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4280 return -EINVAL; in ci_dpm_force_performance_level()
4287 rdev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
4299 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
4301 return -EINVAL; in ci_set_mc_special_registers()
4302 switch (table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers()
4305 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers()
4306 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers()
4307 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4308 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4309 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
4313 return -EINVAL; in ci_set_mc_special_registers()
4316 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers()
4317 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers()
4318 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4319 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4320 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4321 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4322 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
4326 return -EINVAL; in ci_set_mc_special_registers()
4328 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4329 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4330 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4331 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4332 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4333 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
4337 return -EINVAL; in ci_set_mc_special_registers()
4342 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers()
4343 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers()
4344 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4345 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4346 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4350 return -EINVAL; in ci_set_mc_special_registers()
4358 table->last = j; in ci_set_mc_special_registers()
4440 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4441 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
4442 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
4443 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
4444 table->valid_flag |= 1 << i; in ci_set_valid_flag()
4456 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4457 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
4458 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ci_set_s0_mc_reg_index()
4459 address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
4468 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_copy_vbios_mc_reg_table()
4469 return -EINVAL; in ci_copy_vbios_mc_reg_table()
4470 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ci_copy_vbios_mc_reg_table()
4471 return -EINVAL; in ci_copy_vbios_mc_reg_table()
4473 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4474 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_mc_reg_table()
4476 ci_table->last = table->last; in ci_copy_vbios_mc_reg_table()
4478 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4479 ci_table->mc_reg_table_entry[i].mclk_max = in ci_copy_vbios_mc_reg_table()
4480 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_mc_reg_table()
4481 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4482 ci_table->mc_reg_table_entry[i].mc_data[j] = in ci_copy_vbios_mc_reg_table()
4483 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_mc_reg_table()
4485 ci_table->num_entries = table->num_entries; in ci_copy_vbios_mc_reg_table()
4501 ((rdev->pdev->device == 0x67B0) || in ci_register_patching_mc_seq()
4502 (rdev->pdev->device == 0x67B1))) { in ci_register_patching_mc_seq()
4503 for (i = 0; i < table->last; i++) { in ci_register_patching_mc_seq()
4504 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_register_patching_mc_seq()
4505 return -EINVAL; in ci_register_patching_mc_seq()
4506 switch (table->mc_reg_address[i].s1 >> 2) { in ci_register_patching_mc_seq()
4508 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4509 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4510 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4511 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4512 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | in ci_register_patching_mc_seq()
4517 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4518 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4519 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4520 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4521 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4526 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4527 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4528 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4529 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4530 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4535 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4536 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4537 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4538 table->mc_reg_table_entry[k].mc_data[i] = 0; in ci_register_patching_mc_seq()
4542 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4543 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4544 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4545 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4547 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4548 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4549 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4554 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4555 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4556 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4557 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4559 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4560 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4561 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4584 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4590 return -ENOMEM; in ci_initialize_mc_reg_table()
4645 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4646 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4648 return -EINVAL; in ci_populate_mc_reg_addresses()
4649 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4650 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4655 mc_reg_table->last = (u8)i; in ci_populate_mc_reg_addresses()
4668 data->value[i] = cpu_to_be32(entry->mc_data[j]); in ci_convert_mc_registers()
4681 for (i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4682 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4686 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4687 --i; in ci_convert_mc_reg_table_entry_to_smc()
4689 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4690 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4691 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4700 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4702 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4703 &mc_reg_table->data[i]); in ci_convert_mc_reg_table_to_smc()
4711 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4713 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4716 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4719 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4720 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4722 pi->sram_end); in ci_populate_initial_mc_reg_table()
4729 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4732 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4734 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4737 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4739 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4741 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4742 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4760 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()
4761 pcie_speed = state->performance_levels[i].pcie_gen; in ci_get_maximum_link_speed()
4814 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4817 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4819 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4820 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4827 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4837 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4842 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4855 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4877 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
4879 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4881 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4884 return -EINVAL; in ci_set_private_data_variables_based_on_pptable()
4885 if (allowed_sclk_vddc_table->count < 1) in ci_set_private_data_variables_based_on_pptable()
4886 return -EINVAL; in ci_set_private_data_variables_based_on_pptable()
4888 return -EINVAL; in ci_set_private_data_variables_based_on_pptable()
4889 if (allowed_mclk_vddc_table->count < 1) in ci_set_private_data_variables_based_on_pptable()
4890 return -EINVAL; in ci_set_private_data_variables_based_on_pptable()
4892 return -EINVAL; in ci_set_private_data_variables_based_on_pptable()
4893 if (allowed_mclk_vddci_table->count < 1) in ci_set_private_data_variables_based_on_pptable()
4894 return -EINVAL; in ci_set_private_data_variables_based_on_pptable()
4896 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4897 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4898 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; in ci_set_private_data_variables_based_on_pptable()
4900 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4901 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4902 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; in ci_set_private_data_variables_based_on_pptable()
4904 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
4905 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; in ci_set_private_data_variables_based_on_pptable()
4906 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
4907 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; in ci_set_private_data_variables_based_on_pptable()
4908 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4909 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; in ci_set_private_data_variables_based_on_pptable()
4910 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
4911 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; in ci_set_private_data_variables_based_on_pptable()
4919 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4922 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { in ci_patch_with_vddc_leakage()
4923 if (leakage_table->leakage_id[leakage_index] == *vddc) { in ci_patch_with_vddc_leakage()
4924 *vddc = leakage_table->actual_voltage[leakage_index]; in ci_patch_with_vddc_leakage()
4933 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
4936 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { in ci_patch_with_vddci_leakage()
4937 if (leakage_table->leakage_id[leakage_index] == *vddci) { in ci_patch_with_vddci_leakage()
4938 *vddci = leakage_table->actual_voltage[leakage_index]; in ci_patch_with_vddci_leakage()
4950 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4951 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4961 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4962 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4972 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4973 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4983 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4984 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4994 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
4995 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5003 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5004 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5014 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
5015 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()
5023 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5025 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5027 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5029 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5031 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5033 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5035 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5037 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5039 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5041 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5043 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5045 &rdev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5058 pi->mem_gddr5 = true; in ci_get_memory_type()
5060 pi->mem_gddr5 = false; in ci_get_memory_type()
5070 pi->current_rps = *rps; in ci_update_current_ps()
5071 pi->current_ps = *new_ps; in ci_update_current_ps()
5072 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5081 pi->requested_rps = *rps; in ci_update_requested_ps()
5082 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5083 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5089 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5094 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5102 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5124 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_enable()
5128 return -EINVAL; in ci_dpm_enable()
5129 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5137 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5140 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5142 if (pi->dynamic_ss) in ci_dpm_enable()
5144 if (pi->thermal_protection) in ci_dpm_enable()
5174 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5279 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_disable()
5288 if (pi->thermal_protection) in ci_dpm_disable()
5310 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5311 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5315 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5344 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5366 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5412 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in ci_parse_pplib_non_clock_info()
5413 rps->class = le16_to_cpu(non_clock_info->usClassification); in ci_parse_pplib_non_clock_info()
5414 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in ci_parse_pplib_non_clock_info()
5417 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ci_parse_pplib_non_clock_info()
5418 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ci_parse_pplib_non_clock_info()
5420 rps->vclk = 0; in ci_parse_pplib_non_clock_info()
5421 rps->dclk = 0; in ci_parse_pplib_non_clock_info()
5424 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) in ci_parse_pplib_non_clock_info()
5425 rdev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5426 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in ci_parse_pplib_non_clock_info()
5427 rdev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5436 struct ci_pl *pl = &ps->performance_levels[index]; in ci_parse_pplib_clock_info()
5438 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()
5440 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); in ci_parse_pplib_clock_info()
5441 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; in ci_parse_pplib_clock_info()
5442 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); in ci_parse_pplib_clock_info()
5443 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; in ci_parse_pplib_clock_info()
5445 pl->pcie_gen = r600_get_pcie_gen_support(rdev, in ci_parse_pplib_clock_info()
5446 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5447 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5448 clock_info->ci.ucPCIEGen); in ci_parse_pplib_clock_info()
5449 pl->pcie_lane = r600_get_pcie_lane_support(rdev, in ci_parse_pplib_clock_info()
5450 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5451 le16_to_cpu(clock_info->ci.usPCIELane)); in ci_parse_pplib_clock_info()
5453 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { in ci_parse_pplib_clock_info()
5454 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5457 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { in ci_parse_pplib_clock_info()
5458 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5459 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5460 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5464 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in ci_parse_pplib_clock_info()
5465 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5466 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5467 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5468 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5471 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { in ci_parse_pplib_clock_info()
5473 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5474 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5475 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5476 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5477 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5478 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5479 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5480 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5481 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5484 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5485 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5486 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5487 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5488 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5489 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5490 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5491 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5492 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5501 struct radeon_mode_info *mode_info = &rdev->mode_info; in ci_parse_power_table()
5517 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in ci_parse_power_table()
5519 return -EINVAL; in ci_parse_power_table()
5520 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in ci_parse_power_table()
5523 (mode_info->atom_context->bios + data_offset + in ci_parse_power_table()
5524 le16_to_cpu(power_info->pplib.usStateArrayOffset)); in ci_parse_power_table()
5526 (mode_info->atom_context->bios + data_offset + in ci_parse_power_table()
5527 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); in ci_parse_power_table()
5529 (mode_info->atom_context->bios + data_offset + in ci_parse_power_table()
5530 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); in ci_parse_power_table()
5532 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in ci_parse_power_table()
5535 if (!rdev->pm.dpm.ps) in ci_parse_power_table()
5536 return -ENOMEM; in ci_parse_power_table()
5537 power_state_offset = (u8 *)state_array->states; in ci_parse_power_table()
5538 rdev->pm.dpm.num_ps = 0; in ci_parse_power_table()
5539 for (i = 0; i < state_array->ucNumEntries; i++) { in ci_parse_power_table()
5542 non_clock_array_index = power_state->v2.nonClockInfoIndex; in ci_parse_power_table()
5544 &non_clock_info_array->nonClockInfo[non_clock_array_index]; in ci_parse_power_table()
5545 if (!rdev->pm.power_state[i].clock_info) { in ci_parse_power_table()
5546 ret = -EINVAL; in ci_parse_power_table()
5551 ret = -ENOMEM; in ci_parse_power_table()
5554 rdev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5555 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ci_parse_power_table()
5557 non_clock_info_array->ucEntrySize); in ci_parse_power_table()
5559 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in ci_parse_power_table()
5560 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in ci_parse_power_table()
5562 if (clock_array_index >= clock_info_array->ucNumEntries) in ci_parse_power_table()
5567 ((u8 *)&clock_info_array->clockInfo[0] + in ci_parse_power_table()
5568 (clock_array_index * clock_info_array->ucEntrySize)); in ci_parse_power_table()
5570 &rdev->pm.dpm.ps[i], k, in ci_parse_power_table()
5574 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in ci_parse_power_table()
5575 rdev->pm.dpm.num_ps = i + 1; in ci_parse_power_table()
5581 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5583 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; in ci_parse_power_table()
5584 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); in ci_parse_power_table()
5585 sclk |= clock_info->ci.ucEngineClockHigh << 16; in ci_parse_power_table()
5586 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); in ci_parse_power_table()
5587 mclk |= clock_info->ci.ucMemoryClockHigh << 16; in ci_parse_power_table()
5588 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5589 rdev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5595 for (i = 0; i < rdev->pm.dpm.num_ps; i++) in ci_parse_power_table()
5596 kfree(rdev->pm.dpm.ps[i].ps_priv); in ci_parse_power_table()
5597 kfree(rdev->pm.dpm.ps); in ci_parse_power_table()
5604 struct radeon_mode_info *mode_info = &rdev->mode_info; in ci_get_vbios_boot_values()
5610 if (atom_parse_data_header(mode_info->atom_context, index, NULL, in ci_get_vbios_boot_values()
5613 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + in ci_get_vbios_boot_values()
5615 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); in ci_get_vbios_boot_values()
5616 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); in ci_get_vbios_boot_values()
5617 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); in ci_get_vbios_boot_values()
5618 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); in ci_get_vbios_boot_values()
5619 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); in ci_get_vbios_boot_values()
5620 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); in ci_get_vbios_boot_values()
5621 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); in ci_get_vbios_boot_values()
5625 return -EINVAL; in ci_get_vbios_boot_values()
5632 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5633 kfree(rdev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5635 kfree(rdev->pm.dpm.ps); in ci_dpm_fini()
5636 kfree(rdev->pm.dpm.priv); in ci_dpm_fini()
5637 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5650 struct pci_dev *root = rdev->pdev->bus->self; in ci_dpm_init()
5655 return -ENOMEM; in ci_dpm_init()
5656 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5658 if (!pci_is_root_bus(rdev->pdev->bus)) in ci_dpm_init()
5661 pi->sys_pcie_mask = 0; in ci_dpm_init()
5664 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5668 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5671 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5673 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5675 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5676 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5677 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5678 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5680 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5681 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5682 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5683 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5685 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5687 kfree(rdev->pm.dpm.priv); in ci_dpm_init()
5693 kfree(rdev->pm.dpm.priv); in ci_dpm_init()
5699 kfree(rdev->pm.dpm.priv); in ci_dpm_init()
5705 kfree(rdev->pm.dpm.priv); in ci_dpm_init()
5710 pi->dll_default_on = false; in ci_dpm_init()
5711 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5713 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5714 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5715 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5716 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5717 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5718 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5719 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5720 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5722 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5724 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5725 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5726 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5727 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5730 if ((rdev->pdev->device == 0x6658) && in ci_dpm_init()
5731 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) { in ci_dpm_init()
5732 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5735 pi->caps_sclk_ds = true; in ci_dpm_init()
5737 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5738 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5739 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5740 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5744 pi->caps_fps = false; in ci_dpm_init()
5746 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5748 pi->caps_uvd_dpm = true; in ci_dpm_init()
5749 pi->caps_vce_dpm = true; in ci_dpm_init()
5755 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5759 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5761 return -ENOMEM; in ci_dpm_init()
5763 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5764 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5765 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5766 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5767 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5768 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5769 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5770 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5771 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5773 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5774 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5775 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5777 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5778 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5779 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5780 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5782 if (rdev->family == CHIP_HAWAII) { in ci_dpm_init()
5783 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5784 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5785 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5787 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5788 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5789 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5792 pi->uvd_enabled = false; in ci_dpm_init()
5794 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5798 dpm_table->VRHotGpio = gpio.shift; in ci_dpm_init()
5799 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5801 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; in ci_dpm_init()
5802 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5807 dpm_table->AcDcGpio = gpio.shift; in ci_dpm_init()
5808 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5810 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; in ci_dpm_init()
5811 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5843 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5844 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5845 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5847 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5849 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5851 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
5853 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5855 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5857 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
5860 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
5862 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5864 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5866 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
5869 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5872 pi->pcie_performance_request = in ci_dpm_init()
5875 pi->pcie_performance_request = false; in ci_dpm_init()
5878 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, in ci_dpm_init()
5880 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5881 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5882 pi->dynamic_ss = true; in ci_dpm_init()
5884 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5885 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5886 pi->dynamic_ss = true; in ci_dpm_init()
5889 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in ci_dpm_init()
5890 pi->thermal_protection = true; in ci_dpm_init()
5892 pi->thermal_protection = false; in ci_dpm_init()
5894 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5896 pi->uvd_power_gated = false; in ci_dpm_init()
5899 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5900 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5901 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
5902 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()
5904 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5913 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5917 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5918 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5930 r600_dpm_print_class_info(rps->class, rps->class2); in ci_dpm_print_power_state()
5931 r600_dpm_print_cap_info(rps->caps); in ci_dpm_print_power_state()
5932 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ci_dpm_print_power_state()
5933 for (i = 0; i < ps->performance_level_count; i++) { in ci_dpm_print_power_state()
5934 pl = &ps->performance_levels[i]; in ci_dpm_print_power_state()
5936 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); in ci_dpm_print_power_state()
5958 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5961 return requested_state->performance_levels[0].sclk; in ci_dpm_get_sclk()
5963 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in ci_dpm_get_sclk()
5969 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()
5972 return requested_state->performance_levels[0].mclk; in ci_dpm_get_mclk()
5974 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in ci_dpm_get_mclk()