548 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_update_vs_emph()  argument
551 	atombios_dig_transmitter_setup(dp_info->encoder,  in radeon_dp_update_vs_emph()
553 				       0, dp_info->train_set[0]); /* sets all lanes at once */  in radeon_dp_update_vs_emph()
556 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,  in radeon_dp_update_vs_emph()
557 			  dp_info->train_set, dp_info->dp_lane_count);  in radeon_dp_update_vs_emph()
560 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)  in radeon_dp_set_tp()  argument
565 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {  in radeon_dp_set_tp()
577 		atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);  in radeon_dp_set_tp()
587 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,  in radeon_dp_set_tp()
588 					  dp_info->dp_clock, dp_info->enc_id, rtp);  in radeon_dp_set_tp()
592 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);  in radeon_dp_set_tp()
595 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_init()  argument
597 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);  in radeon_dp_link_train_init()
602 	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);  in radeon_dp_link_train_init()
605 	if (dp_info->dpcd[3] & 0x1)  in radeon_dp_link_train_init()
606 		drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
609 		drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
613 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);  in radeon_dp_link_train_init()
616 	tmp = dp_info->dp_lane_count;  in radeon_dp_link_train_init()
617 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in radeon_dp_link_train_init()
619 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);  in radeon_dp_link_train_init()
622 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);  in radeon_dp_link_train_init()
623 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);  in radeon_dp_link_train_init()
626 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)  in radeon_dp_link_train_init()
627 		atombios_dig_encoder_setup(dp_info->encoder,  in radeon_dp_link_train_init()
630 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,  in radeon_dp_link_train_init()
631 					  dp_info->dp_clock, dp_info->enc_id, 0);  in radeon_dp_link_train_init()
634 	drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
641 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_finish()  argument
646 	drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_finish()
651 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)  in radeon_dp_link_train_finish()
652 		atombios_dig_encoder_setup(dp_info->encoder,  in radeon_dp_link_train_finish()
655 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,  in radeon_dp_link_train_finish()
656 					  dp_info->dp_clock, dp_info->enc_id, 0);  in radeon_dp_link_train_finish()
661 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_cr()  argument
667 	radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);  in radeon_dp_link_train_cr()
668 	memset(dp_info->train_set, 0, 4);  in radeon_dp_link_train_cr()
669 	radeon_dp_update_vs_emph(dp_info);  in radeon_dp_link_train_cr()
675 	dp_info->tries = 0;  in radeon_dp_link_train_cr()
678 		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);  in radeon_dp_link_train_cr()
680 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in radeon_dp_link_train_cr()
681 						 dp_info->link_status) <= 0) {  in radeon_dp_link_train_cr()
686 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in radeon_dp_link_train_cr()
691 		for (i = 0; i < dp_info->dp_lane_count; i++) {  in radeon_dp_link_train_cr()
692 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in radeon_dp_link_train_cr()
695 		if (i == dp_info->dp_lane_count) {  in radeon_dp_link_train_cr()
700 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in radeon_dp_link_train_cr()
701 			++dp_info->tries;  in radeon_dp_link_train_cr()
702 			if (dp_info->tries == 5) {  in radeon_dp_link_train_cr()
707 			dp_info->tries = 0;  in radeon_dp_link_train_cr()
709 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in radeon_dp_link_train_cr()
712 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);  in radeon_dp_link_train_cr()
714 		radeon_dp_update_vs_emph(dp_info);  in radeon_dp_link_train_cr()
721 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in radeon_dp_link_train_cr()
722 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in radeon_dp_link_train_cr()
728 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_ce()  argument
732 	if (dp_info->tp3_supported)  in radeon_dp_link_train_ce()
733 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);  in radeon_dp_link_train_ce()
735 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);  in radeon_dp_link_train_ce()
738 	dp_info->tries = 0;  in radeon_dp_link_train_ce()
741 		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);  in radeon_dp_link_train_ce()
743 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in radeon_dp_link_train_ce()
744 						 dp_info->link_status) <= 0) {  in radeon_dp_link_train_ce()
749 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in radeon_dp_link_train_ce()
755 		if (dp_info->tries > 5) {  in radeon_dp_link_train_ce()
761 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);  in radeon_dp_link_train_ce()
763 		radeon_dp_update_vs_emph(dp_info);  in radeon_dp_link_train_ce()
764 		dp_info->tries++;  in radeon_dp_link_train_ce()
772 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in radeon_dp_link_train_ce()
773 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)  in radeon_dp_link_train_ce()
788 	struct radeon_dp_link_train_info dp_info;  in radeon_dp_link_train()  local
809 	dp_info.use_dpencoder = true;  in radeon_dp_link_train()
813 			dp_info.use_dpencoder = false;  in radeon_dp_link_train()
816 	dp_info.enc_id = 0;  in radeon_dp_link_train()
818 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;  in radeon_dp_link_train()
820 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;  in radeon_dp_link_train()
822 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;  in radeon_dp_link_train()
824 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;  in radeon_dp_link_train()
829 			dp_info.tp3_supported = true;  in radeon_dp_link_train()
831 			dp_info.tp3_supported = false;  in radeon_dp_link_train()
833 		dp_info.tp3_supported = false;  in radeon_dp_link_train()
836 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in radeon_dp_link_train()
837 	dp_info.rdev = rdev;  in radeon_dp_link_train()
838 	dp_info.encoder = encoder;  in radeon_dp_link_train()
839 	dp_info.connector = connector;  in radeon_dp_link_train()
840 	dp_info.dp_lane_count = dig_connector->dp_lane_count;  in radeon_dp_link_train()
841 	dp_info.dp_clock = dig_connector->dp_clock;  in radeon_dp_link_train()
842 	dp_info.aux = &radeon_connector->ddc_bus->aux;  in radeon_dp_link_train()
844 	if (radeon_dp_link_train_init(&dp_info))  in radeon_dp_link_train()
846 	if (radeon_dp_link_train_cr(&dp_info))  in radeon_dp_link_train()
848 	if (radeon_dp_link_train_ce(&dp_info))  in radeon_dp_link_train()
851 	if (radeon_dp_link_train_finish(&dp_info))  in radeon_dp_link_train()