Lines Matching +full:pll +full:- +full:mode
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
39 struct drm_display_mode *mode, in atombios_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in atombios_overscan_setup()
62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in atombios_overscan_setup()
65 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in atombios_overscan_setup()
66 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in atombios_overscan_setup()
68 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in atombios_overscan_setup()
69 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in atombios_overscan_setup()
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_overscan_setup()
85 struct drm_device *dev = crtc->dev; in atombios_scaler_setup()
86 struct radeon_device *rdev = dev->dev_private; in atombios_scaler_setup()
91 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
92 /* fixme - fill in enc_priv for atom dac */ in atombios_scaler_setup()
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { in atombios_scaler_setup()
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; in atombios_scaler_setup()
101 tv_std = tv_dac->tv_std; in atombios_scaler_setup()
107 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
142 switch (radeon_crtc->rmx_type) { in atombios_scaler_setup()
160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_scaler_setup()
162 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { in atombios_scaler_setup()
170 struct drm_device *dev = crtc->dev; in atombios_lock_crtc()
171 struct radeon_device *rdev = dev->dev_private; in atombios_lock_crtc()
178 args.ucCRTC = radeon_crtc->crtc_id; in atombios_lock_crtc()
181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_lock_crtc()
187 struct drm_device *dev = crtc->dev; in atombios_enable_crtc()
188 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc()
194 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc()
197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_enable_crtc()
203 struct drm_device *dev = crtc->dev; in atombios_enable_crtc_memreq()
204 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc_memreq()
210 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc_memreq()
213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_enable_crtc_memreq()
229 struct drm_device *dev = crtc->dev; in atombios_blank_crtc()
230 struct radeon_device *rdev = dev->dev_private; in atombios_blank_crtc()
238 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); in atombios_blank_crtc()
239 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); in atombios_blank_crtc()
242 args.ucCRTC = radeon_crtc->crtc_id; in atombios_blank_crtc()
245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_blank_crtc()
248 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); in atombios_blank_crtc()
254 struct drm_device *dev = crtc->dev; in atombios_powergate_crtc()
255 struct radeon_device *rdev = dev->dev_private; in atombios_powergate_crtc()
261 args.ucDispPipeId = radeon_crtc->crtc_id; in atombios_powergate_crtc()
264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_powergate_crtc()
267 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) in atombios_crtc_dpms() argument
269 struct drm_device *dev = crtc->dev; in atombios_crtc_dpms()
270 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_dpms()
273 switch (mode) { in atombios_crtc_dpms()
275 radeon_crtc->enabled = true; in atombios_crtc_dpms()
280 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
287 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
289 if (radeon_crtc->enabled) in atombios_crtc_dpms()
294 radeon_crtc->enabled = false; in atombios_crtc_dpms()
303 struct drm_display_mode *mode) in atombios_set_crtc_dtd_timing() argument
306 struct drm_device *dev = crtc->dev; in atombios_set_crtc_dtd_timing()
307 struct radeon_device *rdev = dev->dev_private; in atombios_set_crtc_dtd_timing()
313 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
315 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
316 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
318 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
320 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing()
322 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_set_crtc_dtd_timing()
324 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); in atombios_set_crtc_dtd_timing()
326 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_set_crtc_dtd_timing()
327 args.ucH_Border = radeon_crtc->h_border; in atombios_set_crtc_dtd_timing()
328 args.ucV_Border = radeon_crtc->v_border; in atombios_set_crtc_dtd_timing()
330 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_set_crtc_dtd_timing()
332 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_set_crtc_dtd_timing()
334 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_set_crtc_dtd_timing()
336 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_set_crtc_dtd_timing()
338 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in atombios_set_crtc_dtd_timing()
340 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_set_crtc_dtd_timing()
344 args.ucCRTC = radeon_crtc->crtc_id; in atombios_set_crtc_dtd_timing()
346 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_set_crtc_dtd_timing()
350 struct drm_display_mode *mode) in atombios_crtc_set_timing() argument
353 struct drm_device *dev = crtc->dev; in atombios_crtc_set_timing()
354 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_timing()
360 args.usH_Total = cpu_to_le16(mode->crtc_htotal); in atombios_crtc_set_timing()
361 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); in atombios_crtc_set_timing()
362 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); in atombios_crtc_set_timing()
364 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_crtc_set_timing()
365 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); in atombios_crtc_set_timing()
366 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); in atombios_crtc_set_timing()
367 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); in atombios_crtc_set_timing()
369 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_crtc_set_timing()
371 args.ucOverscanRight = radeon_crtc->h_border; in atombios_crtc_set_timing()
372 args.ucOverscanLeft = radeon_crtc->h_border; in atombios_crtc_set_timing()
373 args.ucOverscanBottom = radeon_crtc->v_border; in atombios_crtc_set_timing()
374 args.ucOverscanTop = radeon_crtc->v_border; in atombios_crtc_set_timing()
376 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_crtc_set_timing()
378 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_crtc_set_timing()
380 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_crtc_set_timing()
382 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_crtc_set_timing()
384 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in atombios_crtc_set_timing()
386 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_crtc_set_timing()
390 args.ucCRTC = radeon_crtc->crtc_id; in atombios_crtc_set_timing()
392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_crtc_set_timing()
456 * again can cause display problems if the pll is already in atombios_crtc_program_ss()
459 if (ss->percentage == 0) in atombios_crtc_program_ss()
461 if (ss->type & ATOM_EXTERNAL_SS_MASK) in atombios_crtc_program_ss()
464 for (i = 0; i < rdev->num_crtc; i++) { in atombios_crtc_program_ss()
465 if (rdev->mode_info.crtcs[i] && in atombios_crtc_program_ss()
466 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_program_ss()
468 pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_program_ss()
469 /* one other crtc is using this pll don't turn in atombios_crtc_program_ss()
482 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
496 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
497 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
500 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
501 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
515 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
516 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
519 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
520 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
521 args.v1.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
522 args.v1.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
523 args.v1.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
527 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || in atombios_crtc_program_ss()
528 (ss->type & ATOM_EXTERNAL_SS_MASK)) { in atombios_crtc_program_ss()
532 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
533 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
534 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
535 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
536 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
543 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
544 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
545 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; in atombios_crtc_program_ss()
546 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; in atombios_crtc_program_ss()
549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_crtc_program_ss()
558 struct drm_display_mode *mode) in atombios_adjust_pll() argument
561 struct drm_device *dev = crtc->dev; in atombios_adjust_pll()
562 struct radeon_device *rdev = dev->dev_private; in atombios_adjust_pll()
563 struct drm_encoder *encoder = radeon_crtc->encoder; in atombios_adjust_pll()
566 u32 adjusted_clock = mode->clock; in atombios_adjust_pll()
568 u32 dp_clock = mode->clock; in atombios_adjust_pll()
569 u32 clock = mode->clock; in atombios_adjust_pll()
570 int bpc = radeon_crtc->bpc; in atombios_adjust_pll()
571 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); in atombios_adjust_pll()
573 /* reset the pll flags */ in atombios_adjust_pll()
574 radeon_crtc->pll_flags = 0; in atombios_adjust_pll()
577 if ((rdev->family == CHIP_RS600) || in atombios_adjust_pll()
578 (rdev->family == CHIP_RS690) || in atombios_adjust_pll()
579 (rdev->family == CHIP_RS740)) in atombios_adjust_pll()
580 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ in atombios_adjust_pll()
583 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
586 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
588 if (rdev->family < CHIP_RV770) in atombios_adjust_pll()
589 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; in atombios_adjust_pll()
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
594 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) in atombios_adjust_pll()
595 && !radeon_crtc->ss_enabled) in atombios_adjust_pll()
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
597 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) in atombios_adjust_pll()
598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
600 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; in atombios_adjust_pll()
602 if (mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
605 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
608 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_adjust_pll()
613 radeon_connector->con_priv; in atombios_adjust_pll()
615 dp_clock = dig_connector->dp_clock; in atombios_adjust_pll()
620 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in atombios_adjust_pll()
621 if (radeon_crtc->ss_enabled) { in atombios_adjust_pll()
622 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
623 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
624 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
626 rdev->family != CHIP_RS780 && in atombios_adjust_pll()
627 rdev->family != CHIP_RS880) in atombios_adjust_pll()
628 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
634 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ in atombios_adjust_pll()
635 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) in atombios_adjust_pll()
636 adjusted_clock = mode->clock * 2; in atombios_adjust_pll()
637 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_adjust_pll()
638 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; in atombios_adjust_pll()
639 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in atombios_adjust_pll()
640 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; in atombios_adjust_pll()
642 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) in atombios_adjust_pll()
643 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; in atombios_adjust_pll()
644 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) in atombios_adjust_pll()
645 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
648 /* adjust pll for deep color modes */ in atombios_adjust_pll()
676 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_adjust_pll()
688 args.v1.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
690 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
694 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
700 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
703 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
711 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { in atombios_adjust_pll()
712 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_adjust_pll()
713 if (dig->coherent_mode) in atombios_adjust_pll()
727 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
731 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
732 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
733 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in atombios_adjust_pll()
736 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; in atombios_adjust_pll()
738 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()
776 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_set_disp_eng_pll()
812 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_crtc_set_disp_eng_pll()
829 struct drm_device *dev = crtc->dev; in atombios_crtc_program_pll()
830 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_program_pll()
837 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_program_pll()
877 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
890 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
919 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
952 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in atombios_crtc_program_pll()
955 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) in atombios_crtc_prepare_pll() argument
958 struct drm_device *dev = crtc->dev; in atombios_crtc_prepare_pll()
959 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_prepare_pll()
961 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
962 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
964 radeon_crtc->bpc = 8; in atombios_crtc_prepare_pll()
965 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
967 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_crtc_prepare_pll()
968 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in atombios_crtc_prepare_pll()
969 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_crtc_prepare_pll()
971 radeon_get_connector_for_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
975 radeon_connector->con_priv; in atombios_crtc_prepare_pll()
978 /* Assign mode clock for hdmi deep color max clock limit check */ in atombios_crtc_prepare_pll()
979 radeon_connector->pixelclock_for_modeset = mode->clock; in atombios_crtc_prepare_pll()
980 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); in atombios_crtc_prepare_pll()
986 dp_clock = dig_connector->dp_clock / 10; in atombios_crtc_prepare_pll()
988 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
989 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in atombios_crtc_prepare_pll()
994 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
996 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
998 if (!radeon_crtc->ss_enabled) in atombios_crtc_prepare_pll()
999 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1001 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1004 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1006 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1010 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
1015 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1017 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1018 dig->lcd_ss_id, in atombios_crtc_prepare_pll()
1019 mode->clock / 10); in atombios_crtc_prepare_pll()
1021 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1023 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1024 dig->lcd_ss_id); in atombios_crtc_prepare_pll()
1028 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1030 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1032 mode->clock / 10); in atombios_crtc_prepare_pll()
1036 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1038 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1040 mode->clock / 10); in atombios_crtc_prepare_pll()
1048 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); in atombios_crtc_prepare_pll()
1053 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) in atombios_crtc_set_pll() argument
1056 struct drm_device *dev = crtc->dev; in atombios_crtc_set_pll()
1057 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_pll()
1059 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_set_pll()
1060 u32 pll_clock = mode->clock; in atombios_crtc_set_pll()
1061 u32 clock = mode->clock; in atombios_crtc_set_pll()
1063 struct radeon_pll *pll; in atombios_crtc_set_pll() local
1064 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_set_pll()
1069 (radeon_crtc->bpc > 8)) in atombios_crtc_set_pll()
1070 clock = radeon_crtc->adjusted_clock; in atombios_crtc_set_pll()
1072 switch (radeon_crtc->pll_id) { in atombios_crtc_set_pll()
1074 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1077 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1082 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1086 /* update pll params */ in atombios_crtc_set_pll()
1087 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1088 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1089 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1091 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_crtc_set_pll()
1093 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1096 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1099 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1102 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1103 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1105 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1106 encoder_mode, radeon_encoder->encoder_id, clock, in atombios_crtc_set_pll()
1108 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); in atombios_crtc_set_pll()
1110 if (radeon_crtc->ss_enabled) { in atombios_crtc_set_pll()
1115 (u32)radeon_crtc->ss.percentage) / in atombios_crtc_set_pll()
1116 (100 * (u32)radeon_crtc->ss.percentage_divider); in atombios_crtc_set_pll()
1117 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in atombios_crtc_set_pll()
1118 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1120 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in atombios_crtc_set_pll()
1121 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1122 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1124 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1125 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1126 radeon_crtc->ss.step = step_size; in atombios_crtc_set_pll()
1129 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1130 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1139 struct drm_device *dev = crtc->dev; in dce4_crtc_do_set_base()
1140 struct radeon_device *rdev = dev->dev_private; in dce4_crtc_do_set_base()
1153 if (!atomic && !crtc->primary->fb) { in dce4_crtc_do_set_base()
1161 target_fb = crtc->primary->fb; in dce4_crtc_do_set_base()
1166 obj = target_fb->obj[0]; in dce4_crtc_do_set_base()
1178 return -EINVAL; in dce4_crtc_do_set_base()
1185 switch (target_fb->format->format) { in dce4_crtc_do_set_base()
1236 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce4_crtc_do_set_base()
1246 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce4_crtc_do_set_base()
1261 &target_fb->format->format); in dce4_crtc_do_set_base()
1262 return -EINVAL; in dce4_crtc_do_set_base()
1269 if (rdev->family >= CHIP_TAHITI) { in dce4_crtc_do_set_base()
1272 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1275 /* Calculate the macrotile mode index. */ in dce4_crtc_do_set_base()
1277 tileb = 8 * 8 * target_fb->format->cpp[0]; in dce4_crtc_do_set_base()
1285 target_fb->format->cpp[0] * 8, in dce4_crtc_do_set_base()
1287 return -EINVAL; in dce4_crtc_do_set_base()
1290 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()
1292 switch (target_fb->format->cpp[0] * 8) { in dce4_crtc_do_set_base()
1305 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; in dce4_crtc_do_set_base()
1311 if (rdev->family >= CHIP_CAYMAN) in dce4_crtc_do_set_base()
1312 tmp = rdev->config.cayman.tile_config; in dce4_crtc_do_set_base()
1314 tmp = rdev->config.evergreen.tile_config; in dce4_crtc_do_set_base()
1335 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1336 /* XXX need to know more about the surface tiling mode */ in dce4_crtc_do_set_base()
1342 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1343 /* Read the pipe config from the 2D TILED SCANOUT mode. in dce4_crtc_do_set_base()
1346 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
1349 } else if ((rdev->family == CHIP_TAHITI) || in dce4_crtc_do_set_base()
1350 (rdev->family == CHIP_PITCAIRN)) in dce4_crtc_do_set_base()
1352 else if ((rdev->family == CHIP_VERDE) || in dce4_crtc_do_set_base()
1353 (rdev->family == CHIP_OLAND) || in dce4_crtc_do_set_base()
1354 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ in dce4_crtc_do_set_base()
1357 switch (radeon_crtc->crtc_id) { in dce4_crtc_do_set_base()
1383 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1385 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1387 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1389 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1391 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1393 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1394 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1401 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1408 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1409 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1410 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1411 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1412 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1413 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1415 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce4_crtc_do_set_base()
1416 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1417 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1419 if (rdev->family >= CHIP_BONAIRE) in dce4_crtc_do_set_base()
1420 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1421 target_fb->height); in dce4_crtc_do_set_base()
1423 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1424 target_fb->height); in dce4_crtc_do_set_base()
1427 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1429 viewport_w = crtc->mode.hdisplay; in dce4_crtc_do_set_base()
1430 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce4_crtc_do_set_base()
1431 if ((rdev->family >= CHIP_BONAIRE) && in dce4_crtc_do_set_base()
1432 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) in dce4_crtc_do_set_base()
1434 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1438 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1440 if (!atomic && fb && fb != crtc->primary->fb) { in dce4_crtc_do_set_base()
1441 rbo = gem_to_radeon_bo(fb->obj[0]); in dce4_crtc_do_set_base()
1460 struct drm_device *dev = crtc->dev; in avivo_crtc_do_set_base()
1461 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_do_set_base()
1473 if (!atomic && !crtc->primary->fb) { in avivo_crtc_do_set_base()
1481 target_fb = crtc->primary->fb; in avivo_crtc_do_set_base()
1483 obj = target_fb->obj[0]; in avivo_crtc_do_set_base()
1498 return -EINVAL; in avivo_crtc_do_set_base()
1504 switch (target_fb->format->format) { in avivo_crtc_do_set_base()
1552 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in avivo_crtc_do_set_base()
1560 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1572 &target_fb->format->format); in avivo_crtc_do_set_base()
1573 return -EINVAL; in avivo_crtc_do_set_base()
1576 if (rdev->family >= CHIP_R600) { in avivo_crtc_do_set_base()
1589 if (radeon_crtc->crtc_id == 0) in avivo_crtc_do_set_base()
1597 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1599 if (rdev->family >= CHIP_RV770) { in avivo_crtc_do_set_base()
1600 if (radeon_crtc->crtc_id) { in avivo_crtc_do_set_base()
1608 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1611 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1612 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1613 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1614 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1617 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1623 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1624 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1625 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1626 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1627 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1628 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1630 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in avivo_crtc_do_set_base()
1631 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1632 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1634 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1635 target_fb->height); in avivo_crtc_do_set_base()
1638 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1640 viewport_w = crtc->mode.hdisplay; in avivo_crtc_do_set_base()
1641 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in avivo_crtc_do_set_base()
1642 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1646 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in avivo_crtc_do_set_base()
1648 if (!atomic && fb && fb != crtc->primary->fb) { in avivo_crtc_do_set_base()
1649 rbo = gem_to_radeon_bo(fb->obj[0]); in avivo_crtc_do_set_base()
1666 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base()
1667 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base()
1681 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base_atomic()
1682 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base_atomic()
1695 struct drm_device *dev = crtc->dev; in radeon_legacy_atom_fixup()
1696 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_atom_fixup()
1700 switch (radeon_crtc->crtc_id) { in radeon_legacy_atom_fixup()
1717 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1725 struct drm_device *dev = crtc->dev; in radeon_get_pll_use_mask()
1730 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_pll_use_mask()
1735 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_pll_use_mask()
1736 pll_in_use |= (1 << test_radeon_crtc->pll_id); in radeon_get_pll_use_mask()
1742 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1746 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1747 * also in DP mode. For DP, a single PPLL can be used for all DP
1752 struct drm_device *dev = crtc->dev; in radeon_get_shared_dp_ppll()
1753 struct radeon_device *rdev = dev->dev_private; in radeon_get_shared_dp_ppll()
1757 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_shared_dp_ppll()
1761 if (test_radeon_crtc->encoder && in radeon_get_shared_dp_ppll()
1762 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { in radeon_get_shared_dp_ppll()
1765 test_radeon_crtc->pll_id == ATOM_PPLL2) in radeon_get_shared_dp_ppll()
1767 /* for DP use the same PLL for all */ in radeon_get_shared_dp_ppll()
1768 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_shared_dp_ppll()
1769 return test_radeon_crtc->pll_id; in radeon_get_shared_dp_ppll()
1776 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1780 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1786 struct drm_device *dev = crtc->dev; in radeon_get_shared_nondp_ppll()
1787 struct radeon_device *rdev = dev->dev_private; in radeon_get_shared_nondp_ppll()
1792 adjusted_clock = radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1797 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_shared_nondp_ppll()
1801 if (test_radeon_crtc->encoder && in radeon_get_shared_nondp_ppll()
1802 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { in radeon_get_shared_nondp_ppll()
1805 test_radeon_crtc->pll_id == ATOM_PPLL2) in radeon_get_shared_nondp_ppll()
1808 if (test_radeon_crtc->connector == radeon_crtc->connector) { in radeon_get_shared_nondp_ppll()
1809 /* if we are, return that pll */ in radeon_get_shared_nondp_ppll()
1810 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_shared_nondp_ppll()
1811 return test_radeon_crtc->pll_id; in radeon_get_shared_nondp_ppll()
1813 /* for non-DP check the clock */ in radeon_get_shared_nondp_ppll()
1814 test_adjusted_clock = test_radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1815 if ((crtc->mode.clock == test_crtc->mode.clock) && in radeon_get_shared_nondp_ppll()
1817 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && in radeon_get_shared_nondp_ppll()
1818 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) in radeon_get_shared_nondp_ppll()
1819 return test_radeon_crtc->pll_id; in radeon_get_shared_nondp_ppll()
1826 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1830 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1831 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1833 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1834 * as there is no need to program the PLL itself. If we are not able to
1835 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1838 * Asic specific PLL information
1842 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1844 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1847 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1848 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1851 * - PPLL0 is available to all UNIPHY (DP only)
1852 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1855 * - DCPLL is available to all UNIPHY (DP only)
1856 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1859 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1865 struct drm_device *dev = crtc->dev; in radeon_atom_pick_pll()
1866 struct radeon_device *rdev = dev->dev_private; in radeon_atom_pick_pll()
1868 to_radeon_encoder(radeon_crtc->encoder); in radeon_atom_pick_pll()
1870 int pll; in radeon_atom_pick_pll() local
1873 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1874 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1879 pll = radeon_get_shared_dp_ppll(crtc); in radeon_atom_pick_pll()
1880 if (pll != ATOM_PPLL_INVALID) in radeon_atom_pick_pll()
1881 return pll; in radeon_atom_pick_pll()
1885 pll = radeon_get_shared_nondp_ppll(crtc); in radeon_atom_pick_pll()
1886 if (pll != ATOM_PPLL_INVALID) in radeon_atom_pick_pll()
1887 return pll; in radeon_atom_pick_pll()
1890 if ((rdev->family == CHIP_KABINI) || in radeon_atom_pick_pll()
1891 (rdev->family == CHIP_MULLINS)) { in radeon_atom_pick_pll()
1914 radeon_encoder->enc_priv; in radeon_atom_pick_pll()
1916 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && in radeon_atom_pick_pll()
1917 (dig->linkb == false)) in radeon_atom_pick_pll()
1920 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1922 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1927 pll = radeon_get_shared_dp_ppll(crtc); in radeon_atom_pick_pll()
1928 if (pll != ATOM_PPLL_INVALID) in radeon_atom_pick_pll()
1929 return pll; in radeon_atom_pick_pll()
1933 pll = radeon_get_shared_nondp_ppll(crtc); in radeon_atom_pick_pll()
1934 if (pll != ATOM_PPLL_INVALID) in radeon_atom_pick_pll()
1935 return pll; in radeon_atom_pick_pll()
1947 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1948 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1960 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, in radeon_atom_pick_pll()
1970 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1971 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1982 pll = radeon_get_shared_dp_ppll(crtc); in radeon_atom_pick_pll()
1983 if (pll != ATOM_PPLL_INVALID) in radeon_atom_pick_pll()
1984 return pll; in radeon_atom_pick_pll()
1988 pll = radeon_get_shared_nondp_ppll(crtc); in radeon_atom_pick_pll()
1989 if (pll != ATOM_PPLL_INVALID) in radeon_atom_pick_pll()
1990 return pll; in radeon_atom_pick_pll()
2001 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ in radeon_atom_pick_pll()
2003 * the matching btw pll and crtc is done through in radeon_atom_pick_pll()
2005 * pll (1 or 2) to select which register to write. ie if using in radeon_atom_pick_pll()
2010 * same as crtcid or when both pll and crtc are enabled and in radeon_atom_pick_pll()
2013 * So just return crtc id as if crtc and pll were hard linked in radeon_atom_pick_pll()
2016 return radeon_crtc->crtc_id; in radeon_atom_pick_pll()
2024 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2029 rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2031 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2033 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2035 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2041 struct drm_display_mode *mode, in atombios_crtc_mode_set() argument
2046 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_set()
2047 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_mode_set()
2049 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_set()
2052 if (radeon_encoder->active_device & in atombios_crtc_mode_set()
2056 if (!radeon_crtc->adjusted_clock) in atombios_crtc_mode_set()
2057 return -EINVAL; in atombios_crtc_mode_set()
2070 if (radeon_crtc->crtc_id == 0) in atombios_crtc_mode_set()
2075 atombios_overscan_setup(crtc, mode, adjusted_mode); in atombios_crtc_mode_set()
2079 radeon_crtc->hw_mode = *adjusted_mode; in atombios_crtc_mode_set()
2085 const struct drm_display_mode *mode, in atombios_crtc_mode_fixup() argument
2089 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_fixup()
2093 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_crtc_mode_fixup()
2094 if (encoder->crtc == crtc) { in atombios_crtc_mode_fixup()
2095 radeon_crtc->encoder = encoder; in atombios_crtc_mode_fixup()
2096 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); in atombios_crtc_mode_fixup()
2100 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { in atombios_crtc_mode_fixup()
2101 radeon_crtc->encoder = NULL; in atombios_crtc_mode_fixup()
2102 radeon_crtc->connector = NULL; in atombios_crtc_mode_fixup()
2105 if (radeon_crtc->encoder) { in atombios_crtc_mode_fixup()
2107 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_fixup()
2109 radeon_crtc->output_csc = radeon_encoder->output_csc; in atombios_crtc_mode_fixup()
2111 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) in atombios_crtc_mode_fixup()
2115 /* pick pll */ in atombios_crtc_mode_fixup()
2116 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); in atombios_crtc_mode_fixup()
2117 /* if we can't get a PPLL for a non-DP encoder, fail */ in atombios_crtc_mode_fixup()
2118 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && in atombios_crtc_mode_fixup()
2119 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) in atombios_crtc_mode_fixup()
2127 struct drm_device *dev = crtc->dev; in atombios_crtc_prepare()
2128 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_prepare()
2147 struct drm_device *dev = crtc->dev; in atombios_crtc_disable()
2148 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_disable()
2153 if (crtc->primary->fb) { in atombios_crtc_disable()
2157 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); in atombios_crtc_disable()
2168 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2170 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2175 for (i = 0; i < rdev->num_crtc; i++) { in atombios_crtc_disable()
2176 if (rdev->mode_info.crtcs[i] && in atombios_crtc_disable()
2177 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_disable()
2178 i != radeon_crtc->crtc_id && in atombios_crtc_disable()
2179 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
2180 /* one other crtc is using this pll don't turn in atombios_crtc_disable()
2181 * off the pll in atombios_crtc_disable()
2187 switch (radeon_crtc->pll_id) { in atombios_crtc_disable()
2191 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2196 if ((rdev->family == CHIP_ARUBA) || in atombios_crtc_disable()
2197 (rdev->family == CHIP_KAVERI) || in atombios_crtc_disable()
2198 (rdev->family == CHIP_BONAIRE) || in atombios_crtc_disable()
2199 (rdev->family == CHIP_HAWAII)) in atombios_crtc_disable()
2200 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2207 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in atombios_crtc_disable()
2208 radeon_crtc->adjusted_clock = 0; in atombios_crtc_disable()
2209 radeon_crtc->encoder = NULL; in atombios_crtc_disable()
2210 radeon_crtc->connector = NULL; in atombios_crtc_disable()
2228 struct radeon_device *rdev = dev->dev_private; in radeon_atombios_init_crtc()
2231 switch (radeon_crtc->crtc_id) { in radeon_atombios_init_crtc()
2234 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2237 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2240 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2246 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2249 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2253 if (radeon_crtc->crtc_id == 1) in radeon_atombios_init_crtc()
2254 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
2255 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; in radeon_atombios_init_crtc()
2257 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()
2259 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in radeon_atombios_init_crtc()
2260 radeon_crtc->adjusted_clock = 0; in radeon_atombios_init_crtc()
2261 radeon_crtc->encoder = NULL; in radeon_atombios_init_crtc()
2262 radeon_crtc->connector = NULL; in radeon_atombios_init_crtc()
2263 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); in radeon_atombios_init_crtc()