Lines Matching +full:tras +full:- +full:max +full:- +full:ns
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
868 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1654 // =1: other external clock source, which is pre-defined
1702 …// =1: other external clock source, which is pre-defined …
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1830 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
2149 // bit1=0: non-coherent mode
2203 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2246 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTa…
2380 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2528 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2564 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2601 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2639 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2678 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2717 … usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only fo…
2781 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2782 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mod…
2795 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max …
2801 … Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this on…
2806 …dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this…
2857 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
2875 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT…
2876 …CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max H…
2886 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2892 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2893 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
2896 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2905 [31:24]- Reserved
2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2921 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2955 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2963 …AX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3172 // [7:0] - I2C LINE Associate ID
3173 // = 0 - no I2C
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3178 // = 3-7 Reserved for future I2C engines
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3284 // usModeMiscInfo-
3296 //usRefreshRate-
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3523 // Bit7-3: Reserved
3542 …USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link m…
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3585 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
3741 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3744 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
3754 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3812 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
3835 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3839 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3841 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3885 //ucGPIO_ID pre-define id for multiple usage
3967 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3984 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4288 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4341 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4347 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4478 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4480 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4493 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4573 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
4574 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
4575 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
4576 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
4578 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4579 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4580 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4666 …USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse i…
4864 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4889 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4890 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4892 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4895 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4898 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4909 Bit[1]=0: DDR-DLL shut-down feature disabled.
4910 1: DDR-DLL shut-down feature enabled.
4911 Bit[2]=0: DDR-PLL Power down feature disabled.
4912 … 1: DDR-PLL Power down feature enabled.
4930 … GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4931 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4933 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
4934 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
4943 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
5079 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5113 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5114 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5116 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5119 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5122 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5133 Bit[1]=0: DDR-DLL shut-down feature disabled.
5134 1: DDR-DLL shut-down feature enabled.
5135 Bit[2]=0: DDR-PLL Power down feature disabled.
5136 … 1: DDR-PLL Power down feature enabled.
5156 … GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5157 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5159 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
5160 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
5169 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
5179 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5182 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5186 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5190 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5280 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5314 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5315 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5317 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5320 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5323 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5333 Bit[1]=0: DDR-DLL shut-down feature disabled.
5334 1: DDR-DLL shut-down feature enabled.
5335 Bit[2]=0: DDR-PLL Power down feature disabled.
5336 1: DDR-PLL Power down feature enabled.
5356 … GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5357 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
5358 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
5359 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
5374 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
5385 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5389 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5393 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5397 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5417 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
5418 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5419 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
5981 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
5983 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
5984 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
5988 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
5989 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
6369 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
6407 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6408 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6425 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6434 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6435 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6454 UCHAR uctRAS; // tRAS
6484 UCHAR uctRAS; // tRAS
6517 UCHAR uctRAS; // tRAS
6557 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6582 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6603 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6605 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6608 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6613 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6645 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6647 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6650 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6655 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6664 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6676 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6678 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6681 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6686 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6695 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6714 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6716 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6725 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6941 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6942 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
7299 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7300 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7301 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7308 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7309 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7310 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7376 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
7450 // [7:4] - connector type
7451 // = 1 - VGA connector
7452 // = 2 - DVI-I
7453 // = 3 - DVI-D
7454 // = 4 - DVI-A
7455 // = 5 - SVIDEO
7456 // = 6 - COMPOSITE
7457 // = 7 - LVDS
7458 // = 8 - DIGITAL LINK
7459 // = 9 - SCART
7460 // = 0xA - HDMI_type A
7461 // = 0xB - HDMI_type B
7462 // = 0xE - Special case1 (DVI+DIN)
7464 // [3:0] - DAC Associated
7465 // = 0 - no DAC
7466 // = 1 - DACA
7467 // = 2 - DACB
7468 // = 3 - External DAC
7533 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7643 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7653 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
7663 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …