drm/panfrost/panfrost_regs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
12 #define GPU_L2_FEATURES			0x004	/* (RO) Level 2 cache features */
94 #define GPU_SHADER_PRESENT_HI		0x104	/* (RO) Shader core present bitmap, high word */
96 #define GPU_TILER_PRESENT_HI		0x114	/* (RO) Tiler core present bitmap, high word */
98 #define GPU_L2_PRESENT_LO		0x120	/* (RO) Level 2 cache present bitmap, low word */
99 #define GPU_L2_PRESENT_HI		0x124	/* (RO) Level 2 cache present bitmap, high word */
106 #define GPU_STACK_PRESENT_HI		0xE04   /* (RO) Core stack present bitmap, high word */
109 #define SHADER_READY_HI			0x144	/* (RO) Shader core ready bitmap, high word */
112 #define TILER_READY_HI			0x154	/* (RO) Tiler core ready bitmap, high word */
114 #define L2_READY_LO			0x160	/* (RO) Level 2 cache ready bitmap, low word */
115 #define L2_READY_HI			0x164	/* (RO) Level 2 cache ready bitmap, high word */
118 #define STACK_READY_HI			0xE14   /* (RO) Core stack ready bitmap, high word */
122 #define SHADER_PWRON_HI			0x184	/* (WO) Shader core power on bitmap, high word */
125 #define TILER_PWRON_HI			0x194	/* (WO) Tiler core power on bitmap, high word */
127 #define L2_PWRON_LO			0x1A0	/* (WO) Level 2 cache power on bitmap, low word */
128 #define L2_PWRON_HI			0x1A4	/* (WO) Level 2 cache power on bitmap, high word */
131 #define STACK_PWRON_HI			0xE24   /* (RO) Core stack power on bitmap, high word */
135 #define SHADER_PWROFF_HI		0x1C4	/* (WO) Shader core power off bitmap, high word */
138 #define TILER_PWROFF_HI			0x1D4	/* (WO) Tiler core power off bitmap, high word */
140 #define L2_PWROFF_LO			0x1E0	/* (WO) Level 2 cache power off bitmap, low word */
141 #define L2_PWROFF_HI			0x1E4	/* (WO) Level 2 cache power off bitmap, high word */
144 #define STACK_PWROFF_HI			0xE34   /* (RO) Core stack power off bitmap, high word */
148 #define SHADER_PWRTRANS_HI		0x204	/* (RO) Shader core power transition bitmap, high word */
151 #define TILER_PWRTRANS_HI		0x214	/* (RO) Tiler core power transition bitmap, high word */
153 #define L2_PWRTRANS_LO			0x220	/* (RO) Level 2 cache power transition bitmap, low word */
154 #define L2_PWRTRANS_HI			0x224	/* (RO) Level 2 cache power transition bitmap, high word */
157 #define STACK_PWRTRANS_HI		0xE44   /* (RO) Core stack power transition bitmap, high word */
161 #define SHADER_PWRACTIVE_HI		0x244	/* (RO) Shader core active bitmap, high word */
164 #define TILER_PWRACTIVE_HI		0x254	/* (RO) Tiler core active bitmap, high word */
166 #define L2_PWRACTIVE_LO			0x260	/* (RO) Level 2 cache active bitmap, low word */
167 #define L2_PWRACTIVE_HI			0x264	/* (RO) Level 2 cache active bitmap, high word */
287 						   (deprecated - only for use with T60x) */
297 …I(as)		(MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
299 #define AS_MEMATTR_HI(as)		(MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high …
301 …_LOCKADDR_HI(as)		(MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
305 #define AS_FAULTADDRESS_HI(as)		(MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high…
309 …(as)		(MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
311 …EXTRA_HI(as)		(MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */
335 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
336 #define gpu_read(dev, reg) readl(dev->iomem + reg)