Lines Matching refs:mipi_dsi_dcs_write_seq
71 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83); in xpp055c272_init_sequence()
72 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
77 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25); in xpp055c272_init_sequence()
78 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00); in xpp055c272_init_sequence()
79 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF, in xpp055c272_init_sequence()
82 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR, in xpp055c272_init_sequence()
85 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46); in xpp055c272_init_sequence()
86 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b); in xpp055c272_init_sequence()
87 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80); in xpp055c272_init_sequence()
88 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30); in xpp055c272_init_sequence()
89 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEQ, in xpp055c272_init_sequence()
92 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER, in xpp055c272_init_sequence()
95 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff, in xpp055c272_init_sequence()
97 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09); in xpp055c272_init_sequence()
100 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95); in xpp055c272_init_sequence()
101 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP1, in xpp055c272_init_sequence()
110 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP2, in xpp055c272_init_sequence()
119 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGAMMA, in xpp055c272_init_sequence()