23 #define ST7701_CMD2BKX_SEL			0xFF
24 #define ST7701_CMD1				0
26 #define ST7701_CMD2BK_MASK			GENMASK(3, 0)
29 #define ST7701_CMD2_BK0_PVGAMCTRL		0xB0 /* Positive Voltage Gamma Control */
30 #define ST7701_CMD2_BK0_NVGAMCTRL		0xB1 /* Negative Voltage Gamma Control */
31 #define ST7701_CMD2_BK0_LNESET			0xC0 /* Display Line setting */
32 #define ST7701_CMD2_BK0_PORCTRL			0xC1 /* Porch control */
33 #define ST7701_CMD2_BK0_INVSEL			0xC2 /* Inversion selection, Frame Rate Control */
36 #define ST7701_CMD2_BK1_VRHS			0xB0 /* Vop amplitude setting */
37 #define ST7701_CMD2_BK1_VCOM			0xB1 /* VCOM amplitude setting */
38 #define ST7701_CMD2_BK1_VGHSS			0xB2 /* VGH Voltage setting */
39 #define ST7701_CMD2_BK1_TESTCMD			0xB3 /* TEST Command Setting */
40 #define ST7701_CMD2_BK1_VGLS			0xB5 /* VGL Voltage setting */
41 #define ST7701_CMD2_BK1_PWCTLR1			0xB7 /* Power Control 1 */
42 #define ST7701_CMD2_BK1_PWCTLR2			0xB8 /* Power Control 2 */
43 #define ST7701_CMD2_BK1_SPD1			0xC1 /* Source pre_drive timing set1 */
44 #define ST7701_CMD2_BK1_SPD2			0xC2 /* Source EQ2 Setting */
45 #define ST7701_CMD2_BK1_MIPISET1		0xD0 /* MIPI Setting 1 */
49 #define ST7701_CMD2_BK0_GAMCTRL_VC0_MASK	GENMASK(3, 0)
50 #define ST7701_CMD2_BK0_GAMCTRL_VC4_MASK	GENMASK(5, 0)
51 #define ST7701_CMD2_BK0_GAMCTRL_VC8_MASK	GENMASK(5, 0)
52 #define ST7701_CMD2_BK0_GAMCTRL_VC16_MASK	GENMASK(4, 0)
53 #define ST7701_CMD2_BK0_GAMCTRL_VC24_MASK	GENMASK(4, 0)
54 #define ST7701_CMD2_BK0_GAMCTRL_VC52_MASK	GENMASK(3, 0)
55 #define ST7701_CMD2_BK0_GAMCTRL_VC80_MASK	GENMASK(5, 0)
56 #define ST7701_CMD2_BK0_GAMCTRL_VC108_MASK	GENMASK(3, 0)
57 #define ST7701_CMD2_BK0_GAMCTRL_VC147_MASK	GENMASK(3, 0)
58 #define ST7701_CMD2_BK0_GAMCTRL_VC175_MASK	GENMASK(5, 0)
59 #define ST7701_CMD2_BK0_GAMCTRL_VC203_MASK	GENMASK(3, 0)
60 #define ST7701_CMD2_BK0_GAMCTRL_VC231_MASK	GENMASK(4, 0)
61 #define ST7701_CMD2_BK0_GAMCTRL_VC239_MASK	GENMASK(4, 0)
62 #define ST7701_CMD2_BK0_GAMCTRL_VC247_MASK	GENMASK(5, 0)
63 #define ST7701_CMD2_BK0_GAMCTRL_VC251_MASK	GENMASK(5, 0)
64 #define ST7701_CMD2_BK0_GAMCTRL_VC255_MASK	GENMASK(4, 0)
65 #define ST7701_CMD2_BK0_LNESET_LINE_MASK	GENMASK(6, 0)
67 #define ST7701_CMD2_BK0_LNESET_LINEDELTA	GENMASK(1, 0)
68 #define ST7701_CMD2_BK0_PORCTRL_VBP_MASK	GENMASK(7, 0)
69 #define ST7701_CMD2_BK0_PORCTRL_VFP_MASK	GENMASK(7, 0)
71 #define ST7701_CMD2_BK0_INVSEL_NLINV_MASK	GENMASK(2, 0)
72 #define ST7701_CMD2_BK0_INVSEL_RTNI_MASK	GENMASK(4, 0)
75 #define ST7701_CMD2_BK1_VRHA_MASK		GENMASK(7, 0)
76 #define ST7701_CMD2_BK1_VCOM_MASK		GENMASK(7, 0)
77 #define ST7701_CMD2_BK1_VGHSS_MASK		GENMASK(3, 0)
80 #define ST7701_CMD2_BK1_VGLS_MASK		GENMASK(3, 0)
83 #define ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK	GENMASK(1, 0)
85 #define ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK	GENMASK(1, 0)
87 #define ST7701_CMD2_BK1_SPD1_T2D_MASK		GENMASK(3, 0)
89 #define ST7701_CMD2_BK1_SPD2_T3D_MASK		GENMASK(3, 0)
97 	OP_BIAS_OFF = 0,
177 		{ -7060, 0x0 }, { -7470, 0x1 },  in st7701_vgls_map()
178 		{ -7910, 0x2 }, { -8140, 0x3 },  in st7701_vgls_map()
179 		{ -8650, 0x4 }, { -8920, 0x5 },  in st7701_vgls_map()
180 		{ -9210, 0x6 }, { -9510, 0x7 },  in st7701_vgls_map()
181 		{ -9830, 0x8 }, { -10170, 0x9 },  in st7701_vgls_map()
182 		{ -10530, 0xa }, { -10910, 0xb },  in st7701_vgls_map()
183 		{ -11310, 0xc }, { -11730, 0xd },  in st7701_vgls_map()
184 		{ -12200, 0xe }, { -12690, 0xf }  in st7701_vgls_map()
188 	for (i = 0; i < ARRAY_SIZE(map); i++)  in st7701_vgls_map()
192 	return 0;  in st7701_vgls_map()
204 	ST7701_WRITE(st7701, ST7701_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val);  in st7701_switch_cmd_bkx()
214 	ST7701_WRITE(st7701, MIPI_DCS_SOFT_RESET, 0x00);  in st7701_init_sequence()
219 	ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);  in st7701_init_sequence()
224 	st7701_switch_cmd_bkx(st7701, true, 0);  in st7701_init_sequence()
232 	 * Line[6:0]: select number of vertical lines of the TFT matrix in  in st7701_init_sequence()
235 	 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected  in st7701_init_sequence()
236 	 *                  using Line[6:0]  in st7701_init_sequence()
239 	 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0)  in st7701_init_sequence()
243 		   (linecountrem2 ? ST7701_CMD2_BK0_LNESET_LDE_EN : 0),  in st7701_init_sequence()
252 	 * PCLK = 512 + (RTNI[4:0] * 16)  in st7701_init_sequence()
265 	/* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */  in st7701_init_sequence()
270 	/* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */  in st7701_init_sequence()
275 	/* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */  in st7701_init_sequence()
298 	/* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */  in st7701_init_sequence()
305 	/* T2D = 0.2us * T2D[3:0] */  in st7701_init_sequence()
311 	/* T3D = 4us + (0.8us * T3D[3:0]) */  in st7701_init_sequence()
319 		   (desc->eot_en ? ST7701_CMD2_BK1_MIPISET1_EOT_EN : 0));  in st7701_init_sequence()
328 	ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);  in ts8550b_gip_sequence()
329 	ST7701_WRITE(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,  in ts8550b_gip_sequence()
330 		   0x00, 0x00, 0x44, 0x44);  in ts8550b_gip_sequence()
331 	ST7701_WRITE(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,  in ts8550b_gip_sequence()
332 		   0x00, 0x65, 0x00, 0x67, 0x00, 0x00);  in ts8550b_gip_sequence()
333 	ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);  in ts8550b_gip_sequence()
334 	ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);  in ts8550b_gip_sequence()
335 	ST7701_WRITE(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,  in ts8550b_gip_sequence()
336 		   0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);  in ts8550b_gip_sequence()
337 	ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);  in ts8550b_gip_sequence()
338 	ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);  in ts8550b_gip_sequence()
339 	ST7701_WRITE(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,  in ts8550b_gip_sequence()
340 		   0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);  in ts8550b_gip_sequence()
341 	ST7701_WRITE(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);  in ts8550b_gip_sequence()
342 	ST7701_WRITE(st7701, 0xEC, 0x00, 0x00);  in ts8550b_gip_sequence()
343 	ST7701_WRITE(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,  in ts8550b_gip_sequence()
344 		   0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);  in ts8550b_gip_sequence()
349 	ST7701_WRITE(st7701, 0xEE, 0x42);  in dmt028vghmcmi_1a_gip_sequence()
350 	ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);  in dmt028vghmcmi_1a_gip_sequence()
352 	ST7701_WRITE(st7701, 0xE1,  in dmt028vghmcmi_1a_gip_sequence()
353 		   0x04, 0xA0, 0x06, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
354 			   0x05, 0xA0, 0x07, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
355 			   0x00, 0x44, 0x44);  in dmt028vghmcmi_1a_gip_sequence()
356 	ST7701_WRITE(st7701, 0xE2,  in dmt028vghmcmi_1a_gip_sequence()
357 		   0x00, 0x00, 0x00, 0x00,  in dmt028vghmcmi_1a_gip_sequence()
358 			   0x00, 0x00, 0x00, 0x00,  in dmt028vghmcmi_1a_gip_sequence()
359 			   0x00, 0x00, 0x00, 0x00);  in dmt028vghmcmi_1a_gip_sequence()
360 	ST7701_WRITE(st7701, 0xE3,  in dmt028vghmcmi_1a_gip_sequence()
361 		   0x00, 0x00, 0x22, 0x22);  in dmt028vghmcmi_1a_gip_sequence()
362 	ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);  in dmt028vghmcmi_1a_gip_sequence()
363 	ST7701_WRITE(st7701, 0xE5,  in dmt028vghmcmi_1a_gip_sequence()
364 		   0x0C, 0x90, 0xA0, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
365 			   0x0E, 0x92, 0xA0, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
366 			   0x08, 0x8C, 0xA0, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
367 			   0x0A, 0x8E, 0xA0, 0xA0);  in dmt028vghmcmi_1a_gip_sequence()
368 	ST7701_WRITE(st7701, 0xE6,  in dmt028vghmcmi_1a_gip_sequence()
369 		   0x00, 0x00, 0x22, 0x22);  in dmt028vghmcmi_1a_gip_sequence()
370 	ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);  in dmt028vghmcmi_1a_gip_sequence()
371 	ST7701_WRITE(st7701, 0xE8,  in dmt028vghmcmi_1a_gip_sequence()
372 		   0x0D, 0x91, 0xA0, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
373 			   0x0F, 0x93, 0xA0, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
374 			   0x09, 0x8D, 0xA0, 0xA0,  in dmt028vghmcmi_1a_gip_sequence()
375 			   0x0B, 0x8F, 0xA0, 0xA0);  in dmt028vghmcmi_1a_gip_sequence()
376 	ST7701_WRITE(st7701, 0xEB,  in dmt028vghmcmi_1a_gip_sequence()
377 		   0x00, 0x00, 0xE4, 0xE4,  in dmt028vghmcmi_1a_gip_sequence()
378 			   0x44, 0x00, 0x00);  in dmt028vghmcmi_1a_gip_sequence()
379 	ST7701_WRITE(st7701, 0xED,  in dmt028vghmcmi_1a_gip_sequence()
380 		   0xFF, 0xF5, 0x47, 0x6F,  in dmt028vghmcmi_1a_gip_sequence()
381 			   0x0B, 0xA1, 0xAB, 0xFF,  in dmt028vghmcmi_1a_gip_sequence()
382 			   0xFF, 0xBA, 0x1A, 0xB0,  in dmt028vghmcmi_1a_gip_sequence()
383 			   0xF6, 0x74, 0x5F, 0xFF);  in dmt028vghmcmi_1a_gip_sequence()
384 	ST7701_WRITE(st7701, 0xEF,  in dmt028vghmcmi_1a_gip_sequence()
385 		   0x08, 0x08, 0x08, 0x40,  in dmt028vghmcmi_1a_gip_sequence()
386 			   0x3F, 0x64);  in dmt028vghmcmi_1a_gip_sequence()
388 	st7701_switch_cmd_bkx(st7701, false, 0);  in dmt028vghmcmi_1a_gip_sequence()
391 	ST7701_WRITE(st7701, 0xE6, 0x7C);  in dmt028vghmcmi_1a_gip_sequence()
392 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E);  in dmt028vghmcmi_1a_gip_sequence()
394 	st7701_switch_cmd_bkx(st7701, false, 0);  in dmt028vghmcmi_1a_gip_sequence()
395 	ST7701_WRITE(st7701, 0x11);  in dmt028vghmcmi_1a_gip_sequence()
399 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C);  in dmt028vghmcmi_1a_gip_sequence()
401 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);  in dmt028vghmcmi_1a_gip_sequence()
403 	st7701_switch_cmd_bkx(st7701, false, 0);  in dmt028vghmcmi_1a_gip_sequence()
404 	ST7701_WRITE(st7701, 0x11);  in dmt028vghmcmi_1a_gip_sequence()
406 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);  in dmt028vghmcmi_1a_gip_sequence()
408 	st7701_switch_cmd_bkx(st7701, false, 0);  in dmt028vghmcmi_1a_gip_sequence()
410 	ST7701_WRITE(st7701, 0x3A, 0x70);  in dmt028vghmcmi_1a_gip_sequence()
419 	ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);  in kd50t048a_gip_sequence()
420 	ST7701_WRITE(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,  in kd50t048a_gip_sequence()
421 		   0x00, 0x00, 0x33, 0x33);  in kd50t048a_gip_sequence()
422 	ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in kd50t048a_gip_sequence()
423 		   0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in kd50t048a_gip_sequence()
424 	ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);  in kd50t048a_gip_sequence()
425 	ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);  in kd50t048a_gip_sequence()
426 	ST7701_WRITE(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,  in kd50t048a_gip_sequence()
427 		   0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0);  in kd50t048a_gip_sequence()
428 	ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);  in kd50t048a_gip_sequence()
429 	ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);  in kd50t048a_gip_sequence()
430 	ST7701_WRITE(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,  in kd50t048a_gip_sequence()
431 		   0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0);  in kd50t048a_gip_sequence()
432 	ST7701_WRITE(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);  in kd50t048a_gip_sequence()
433 	ST7701_WRITE(st7701, 0xEC, 0x02, 0x01);  in kd50t048a_gip_sequence()
434 	ST7701_WRITE(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,  in kd50t048a_gip_sequence()
435 		   0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA);  in kd50t048a_gip_sequence()
441 	ST7701_WRITE(st7701, 0xEF, 0x08);  in rg_arc_gip_sequence()
442 	st7701_switch_cmd_bkx(st7701, true, 0);  in rg_arc_gip_sequence()
443 	ST7701_WRITE(st7701, 0xC7, 0x04);  in rg_arc_gip_sequence()
444 	ST7701_WRITE(st7701, 0xCC, 0x38);  in rg_arc_gip_sequence()
446 	ST7701_WRITE(st7701, 0xB9, 0x10);  in rg_arc_gip_sequence()
447 	ST7701_WRITE(st7701, 0xBC, 0x03);  in rg_arc_gip_sequence()
448 	ST7701_WRITE(st7701, 0xC0, 0x89);  in rg_arc_gip_sequence()
449 	ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);  in rg_arc_gip_sequence()
450 	ST7701_WRITE(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,  in rg_arc_gip_sequence()
451 		   0x00, 0x00, 0x20, 0x20);  in rg_arc_gip_sequence()
452 	ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in rg_arc_gip_sequence()
453 		   0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in rg_arc_gip_sequence()
454 	ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00);  in rg_arc_gip_sequence()
455 	ST7701_WRITE(st7701, 0xE4, 0x22, 0x00);  in rg_arc_gip_sequence()
456 	ST7701_WRITE(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0,  in rg_arc_gip_sequence()
457 		   0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in rg_arc_gip_sequence()
458 	ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00);  in rg_arc_gip_sequence()
459 	ST7701_WRITE(st7701, 0xE7, 0x22, 0x00);  in rg_arc_gip_sequence()
460 	ST7701_WRITE(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0,  in rg_arc_gip_sequence()
461 		   0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in rg_arc_gip_sequence()
462 	ST7701_WRITE(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00);  in rg_arc_gip_sequence()
463 	ST7701_WRITE(st7701, 0xEC, 0x00, 0x00);  in rg_arc_gip_sequence()
464 	ST7701_WRITE(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF,  in rg_arc_gip_sequence()
465 		   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB0, 0x54, 0xAF);  in rg_arc_gip_sequence()
466 	ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);  in rg_arc_gip_sequence()
467 	st7701_switch_cmd_bkx(st7701, false, 0);  in rg_arc_gip_sequence()
468 	ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17);  in rg_arc_gip_sequence()
469 	ST7701_WRITE(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77);  in rg_arc_gip_sequence()
470 	ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);  in rg_arc_gip_sequence()
477 	ST7701_WRITE(st7701, 0xEF, 0x08);  in rg28xx_gip_sequence()
479 	st7701_switch_cmd_bkx(st7701, true, 0);  in rg28xx_gip_sequence()
480 	ST7701_WRITE(st7701, 0xC3, 0x02, 0x10, 0x02);  in rg28xx_gip_sequence()
481 	ST7701_WRITE(st7701, 0xC7, 0x04);  in rg28xx_gip_sequence()
482 	ST7701_WRITE(st7701, 0xCC, 0x10);  in rg28xx_gip_sequence()
485 	ST7701_WRITE(st7701, 0xEE, 0x42);  in rg28xx_gip_sequence()
486 	ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);  in rg28xx_gip_sequence()
488 	ST7701_WRITE(st7701, 0xE1, 0x04, 0xA0, 0x06, 0xA0, 0x05, 0xA0, 0x07, 0xA0,  in rg28xx_gip_sequence()
489 		   0x00, 0x44, 0x44);  in rg28xx_gip_sequence()
490 	ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in rg28xx_gip_sequence()
491 		   0x00, 0x00, 0x00, 0x00);  in rg28xx_gip_sequence()
492 	ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x22, 0x22);  in rg28xx_gip_sequence()
493 	ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);  in rg28xx_gip_sequence()
494 	ST7701_WRITE(st7701, 0xE5, 0x0C, 0x90, 0xA0, 0xA0, 0x0E, 0x92, 0xA0, 0xA0,  in rg28xx_gip_sequence()
495 		   0x08, 0x8C, 0xA0, 0xA0, 0x0A, 0x8E, 0xA0, 0xA0);  in rg28xx_gip_sequence()
496 	ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x22, 0x22);  in rg28xx_gip_sequence()
497 	ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);  in rg28xx_gip_sequence()
498 	ST7701_WRITE(st7701, 0xE8, 0x0D, 0x91, 0xA0, 0xA0, 0x0F, 0x93, 0xA0, 0xA0,  in rg28xx_gip_sequence()
499 		   0x09, 0x8D, 0xA0, 0xA0, 0x0B, 0x8F, 0xA0, 0xA0);  in rg28xx_gip_sequence()
500 	ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x44, 0x00, 0x40);  in rg28xx_gip_sequence()
501 	ST7701_WRITE(st7701, 0xED, 0xFF, 0xF5, 0x47, 0x6F, 0x0B, 0xA1, 0xBA, 0xFF,  in rg28xx_gip_sequence()
502 		   0xFF, 0xAB, 0x1A, 0xB0, 0xF6, 0x74, 0x5F, 0xFF);  in rg28xx_gip_sequence()
503 	ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);  in rg28xx_gip_sequence()
505 	st7701_switch_cmd_bkx(st7701, false, 0);  in rg28xx_gip_sequence()
508 	ST7701_WRITE(st7701, 0xE6, 0x16);  in rg28xx_gip_sequence()
509 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E);  in rg28xx_gip_sequence()
511 	st7701_switch_cmd_bkx(st7701, false, 0);  in rg28xx_gip_sequence()
512 	ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x10);  in rg28xx_gip_sequence()
517 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C);  in rg28xx_gip_sequence()
519 	ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);  in rg28xx_gip_sequence()
520 	st7701_switch_cmd_bkx(st7701, false, 0);  in rg28xx_gip_sequence()
528 	gpiod_set_value(st7701->reset, 0);  in st7701_prepare()
532 	if (ret < 0)  in st7701_prepare()
545 	st7701_switch_cmd_bkx(st7701, false, 0);  in st7701_prepare()
547 	return 0;  in st7701_prepare()
554 	ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);  in st7701_enable()
556 	return 0;  in st7701_enable()
563 	ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);  in st7701_disable()
565 	return 0;  in st7701_disable()
572 	ST7701_WRITE(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);  in st7701_unprepare()
576 	gpiod_set_value(st7701->reset, 0);  in st7701_unprepare()
591 	return 0;  in st7701_unprepare()
666 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
667 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
668 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
669 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
670 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
671 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
672 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
674 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
675 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
676 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
677 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
678 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
680 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
681 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
682 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
683 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
684 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
686 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
687 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
688 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
689 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
690 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
691 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
692 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
695 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
696 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
697 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
698 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
699 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
700 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
701 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
703 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
704 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
705 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
706 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
707 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
709 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
710 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
711 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
712 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
713 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
715 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
716 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
717 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
718 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
719 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
720 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
721 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
767 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
768 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
769 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
770 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
771 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
772 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
773 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
775 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
776 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
777 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
778 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
779 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
781 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
782 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
783 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
784 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
785 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
787 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
788 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
789 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
790 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
791 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
792 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
793 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
796 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
797 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
798 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
799 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
800 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
801 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
802 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
804 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
805 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
806 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
807 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
808 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
810 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
811 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
812 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
813 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
814 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
816 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
817 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
818 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
819 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
820 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
821 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
822 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
863 	.panel_sleep_delay = 0,
866 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
867 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
868 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
869 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
870 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
871 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
872 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
874 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
875 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
876 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
877 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
878 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
880 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
881 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
882 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
883 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
884 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
886 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
888 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
889 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
890 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
891 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
892 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
895 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
896 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
897 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
898 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
899 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
900 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
901 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
903 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
904 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
905 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
906 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
907 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
909 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
910 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
911 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
912 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
913 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
915 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
917 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
918 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
919 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
920 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
921 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
965 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
966 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
967 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
968 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
969 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
970 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d),
971 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
973 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
974 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12),
975 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
976 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
977 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a),
979 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
980 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25),
981 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
982 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
983 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03),
985 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
986 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
987 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
988 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
989 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
990 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
991 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
994 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
995 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
996 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
997 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
998 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
999 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e),
1000 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
1002 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1003 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1004 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
1005 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
1006 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
1008 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
1009 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26),
1010 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
1011 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1012 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15),
1014 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
1015 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1016 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
1017 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1018 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
1019 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1020 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
1022 	.nlinv = 0,
1065 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1066 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1067 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1068 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
1069 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1070 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
1071 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
1073 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1074 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1075 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
1076 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
1077 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
1079 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
1080 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
1081 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
1082 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1083 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
1085 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
1086 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1087 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
1088 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1089 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
1090 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1091 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1094 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1095 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1096 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1097 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
1098 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1099 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
1100 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
1102 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1103 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1104 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
1105 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
1106 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
1108 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
1109 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
1110 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
1111 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1112 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
1114 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
1115 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1116 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
1117 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1118 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
1119 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1120 		CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1161 	st7701->supplies[0].supply = "VCC";  in st7701_probe()
1166 	if (ret < 0)  in st7701_probe()
1176 	if (ret < 0)  in st7701_probe()
1229 	return 0;  in st7701_dsi_probe()
1254 	return 0;  in st7701_spi_probe()
1320 	return 0;  in st7701_driver_init()