36 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in boe_tv101wum_ll2_reset()
40 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in boe_tv101wum_ll2_reset()
56 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e);  in boe_tv101wum_ll2_on()
57 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22,  in boe_tv101wum_ll2_on()
58 				     0x6d, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00);  in boe_tv101wum_ll2_on()
59 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23);  in boe_tv101wum_ll2_on()
60 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00);  in boe_tv101wum_ll2_on()
61 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00);  in boe_tv101wum_ll2_on()
62 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19);  in boe_tv101wum_ll2_on()
63 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38);  in boe_tv101wum_ll2_on()
65 	mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0c);  in boe_tv101wum_ll2_on()
66 	mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0xfd);  in boe_tv101wum_ll2_on()
67 	mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x00);  in boe_tv101wum_ll2_on()
91 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5a);  in boe_tv101wum_ll2_off()
92 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5a);  in boe_tv101wum_ll2_off()
104 	if (ret < 0)  in boe_tv101wum_ll2_prepare()
110 	if (ret < 0) {  in boe_tv101wum_ll2_prepare()
117 	return 0;  in boe_tv101wum_ll2_prepare()
132 	return 0;  in boe_tv101wum_ll2_unprepare()
177 	if (ret < 0)  in boe_tv101wum_ll2_probe()
204 	if (ret < 0) {  in boe_tv101wum_ll2_probe()
209 	return 0;  in boe_tv101wum_ll2_probe()
218 	if (ret < 0)  in boe_tv101wum_ll2_remove()