165 static void dmm_write(struct dmm *dmm, u32 val, u32 reg)  in dmm_write()  function
281 	dmm_write(dmm, status, DMM_PAT_IRQSTATUS);  in omap_dmm_irq_handler()
417 	dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);  in dmm_txn_commit()
433 	dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);  in dmm_txn_commit()
734 		dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_CLR);  in omap_dmm_remove()
854 	dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__0);  in omap_dmm_probe()
855 	dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__1);  in omap_dmm_probe()
856 	dmm_write(omap_dmm, 0x80808080, DMM_PAT_VIEW_MAP__0);  in omap_dmm_probe()
857 	dmm_write(omap_dmm, 0x80000000, DMM_PAT_VIEW_MAP_BASE);  in omap_dmm_probe()
858 	dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__0);  in omap_dmm_probe()
859 	dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__1);  in omap_dmm_probe()
969 	dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_SET);  in omap_dmm_probe()