112 		return 1;  in dss_pll_get_clkout_idx_for_src()
184 	out_min = out_min ? out_min : 1;  in dss_pll_hsdiv_calc_a()
187 	m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);  in dss_pll_hsdiv_calc_a()
221 	n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);  in dss_pll_calc_a()
223 	n_inc = 1;  in dss_pll_calc_a()
230 		n_inc = -1;  in dss_pll_calc_a()
239 				1ul);  in dss_pll_calc_a()
243 		m_inc = 1;  in dss_pll_calc_a()
250 			m_inc = -1;  in dss_pll_calc_a()
291 		m2 = 1;  in dss_pll_calc_b()
342 	/* then loop for 500ms, sleeping for 1ms in between */  in wait_for_bit_change()
360 	if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)  in dss_pll_wait_reset_done()
390 	 * PLL_STATUS[1] = 1  PLL_LOCK  in pll_is_locked()
391 	 * PLL_STATUS[0] = 1  PLL_CTRL_RESET_DONE  in pll_is_locked()
402 	u32 l;  in dss_pll_write_config_type_a()  local
404 	l = 0;  in dss_pll_write_config_type_a()
406 		l = FLD_MOD(l, 1, 0, 0);		/* PLL_STOPMODE */  in dss_pll_write_config_type_a()
407 	l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb);	/* PLL_REGN */  in dss_pll_write_config_type_a()
408 	l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb);		/* PLL_REGM */  in dss_pll_write_config_type_a()
410 	l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,  in dss_pll_write_config_type_a()
413 	l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,  in dss_pll_write_config_type_a()
414 			hw->mX_msb[1], hw->mX_lsb[1]);  in dss_pll_write_config_type_a()
415 	writel_relaxed(l, base + PLL_CONFIGURATION1);  in dss_pll_write_config_type_a()
417 	l = 0;  in dss_pll_write_config_type_a()
419 	l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,  in dss_pll_write_config_type_a()
422 	l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,  in dss_pll_write_config_type_a()
424 	writel_relaxed(l, base + PLL_CONFIGURATION3);  in dss_pll_write_config_type_a()
426 	l = readl_relaxed(base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
434 		l = FLD_MOD(l, f, 4, 1);	/* PLL_FREQSEL */  in dss_pll_write_config_type_a()
438 		l = FLD_MOD(l, f, 3, 1);	/* PLL_SELFREQDCO */  in dss_pll_write_config_type_a()
440 	l = FLD_MOD(l, 1, 13, 13);		/* PLL_REFEN */  in dss_pll_write_config_type_a()
441 	l = FLD_MOD(l, 0, 14, 14);		/* PHY_CLKINEN */  in dss_pll_write_config_type_a()
442 	l = FLD_MOD(l, 0, 16, 16);		/* M4_CLOCK_EN */  in dss_pll_write_config_type_a()
443 	l = FLD_MOD(l, 0, 18, 18);		/* M5_CLOCK_EN */  in dss_pll_write_config_type_a()
444 	l = FLD_MOD(l, 1, 20, 20);		/* HSDIVBYPASS */  in dss_pll_write_config_type_a()
446 		l = FLD_MOD(l, 3, 22, 21);	/* REFSEL = sysclk */  in dss_pll_write_config_type_a()
447 	l = FLD_MOD(l, 0, 23, 23);		/* M6_CLOCK_EN */  in dss_pll_write_config_type_a()
448 	l = FLD_MOD(l, 0, 25, 25);		/* M7_CLOCK_EN */  in dss_pll_write_config_type_a()
449 	writel_relaxed(l, base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
463 			writel_relaxed(1, base + PLL_GO);	/* PLL_GO */  in dss_pll_write_config_type_a()
472 			l = readl_relaxed(base + PLL_STATUS);  in dss_pll_write_config_type_a()
474 			if (pll_is_locked(l) &&  in dss_pll_write_config_type_a()
486 		writel_relaxed(1, base + PLL_GO);	/* PLL_GO */  in dss_pll_write_config_type_a()
494 		if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {  in dss_pll_write_config_type_a()
501 	l = readl_relaxed(base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
502 	l = FLD_MOD(l, 1, 14, 14);			/* PHY_CLKINEN */  in dss_pll_write_config_type_a()
503 	l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16);	/* M4_CLOCK_EN */  in dss_pll_write_config_type_a()
504 	l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18);	/* M5_CLOCK_EN */  in dss_pll_write_config_type_a()
505 	l = FLD_MOD(l, 0, 20, 20);			/* HSDIVBYPASS */  in dss_pll_write_config_type_a()
506 	l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23);	/* M6_CLOCK_EN */  in dss_pll_write_config_type_a()
507 	l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25);	/* M7_CLOCK_EN */  in dss_pll_write_config_type_a()
508 	writel_relaxed(l, base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
512 		(cinfo->mX[1] ? BIT(8) : 0) |  in dss_pll_write_config_type_a()
529 	u32 l;  in dss_pll_write_config_type_b()  local
531 	l = 0;  in dss_pll_write_config_type_b()
532 	l = FLD_MOD(l, cinfo->m, 20, 9);	/* PLL_REGM */  in dss_pll_write_config_type_b()
533 	l = FLD_MOD(l, cinfo->n - 1, 8, 1);	/* PLL_REGN */  in dss_pll_write_config_type_b()
534 	writel_relaxed(l, base + PLL_CONFIGURATION1);  in dss_pll_write_config_type_b()
536 	l = readl_relaxed(base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_b()
537 	l = FLD_MOD(l, 0x0, 12, 12);	/* PLL_HIGHFREQ divide by 2 */  in dss_pll_write_config_type_b()
538 	l = FLD_MOD(l, 0x1, 13, 13);	/* PLL_REFEN */  in dss_pll_write_config_type_b()
539 	l = FLD_MOD(l, 0x0, 14, 14);	/* PHY_CLKINEN */  in dss_pll_write_config_type_b()
541 		l = FLD_MOD(l, 0x3, 22, 21);	/* REFSEL = SYSCLK */  in dss_pll_write_config_type_b()
545 		l = FLD_MOD(l, 0x4, 3, 1);  in dss_pll_write_config_type_b()
547 		l = FLD_MOD(l, 0x2, 3, 1);  in dss_pll_write_config_type_b()
548 	writel_relaxed(l, base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_b()
550 	l = readl_relaxed(base + PLL_CONFIGURATION3);  in dss_pll_write_config_type_b()
551 	l = FLD_MOD(l, cinfo->sd, 17, 10);	/* PLL_REGSD */  in dss_pll_write_config_type_b()
552 	writel_relaxed(l, base + PLL_CONFIGURATION3);  in dss_pll_write_config_type_b()
554 	l = readl_relaxed(base + PLL_CONFIGURATION4);  in dss_pll_write_config_type_b()
555 	l = FLD_MOD(l, cinfo->mX[0], 24, 18);	/* PLL_REGM2 */  in dss_pll_write_config_type_b()
556 	l = FLD_MOD(l, cinfo->mf, 17, 0);	/* PLL_REGM_F */  in dss_pll_write_config_type_b()
557 	writel_relaxed(l, base + PLL_CONFIGURATION4);  in dss_pll_write_config_type_b()
559 	writel_relaxed(1, base + PLL_GO);	/* PLL_GO */  in dss_pll_write_config_type_b()
566 	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {  in dss_pll_write_config_type_b()