Lines Matching +full:4 +full:- +full:temp
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
13 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
31 /* Not really a debug register, more a low-level control register */
58 u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
69 if (msg.len > CEC_MAX_MSG_SIZE - 2) in hdmi_cec_received_msg()
70 msg.len = CEC_MAX_MSG_SIZE - 2; in hdmi_cec_received_msg()
71 msg.msg[0] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
73 msg.msg[1] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
76 unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4; in hdmi_cec_received_msg()
79 hdmi_read_reg(core->base, reg); in hdmi_cec_received_msg()
82 cec_received_msg(core->adap, &msg); in hdmi_cec_received_msg()
85 hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1); in hdmi_cec_received_msg()
87 while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1) in hdmi_cec_received_msg()
90 * Re-read the count register and loop to see if there are in hdmi_cec_received_msg()
93 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
99 u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0); in hdmi4_cec_irq()
100 u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1); in hdmi4_cec_irq()
102 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0); in hdmi4_cec_irq()
103 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1); in hdmi4_cec_irq()
106 cec_transmit_done(core->adap, CEC_TX_STATUS_OK, in hdmi4_cec_irq()
108 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
110 u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3); in hdmi4_cec_irq()
112 cec_transmit_done(core->adap, in hdmi4_cec_irq()
115 0, (dbg3 >> 4) & 7, 0, 0); in hdmi4_cec_irq()
116 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi4_cec_irq()
126 int temp; in hdmi_cec_clear_tx_fifo() local
128 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); in hdmi_cec_clear_tx_fifo()
130 temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3); in hdmi_cec_clear_tx_fifo()
131 if (FLD_GET(temp, 7, 7) == 0) in hdmi_cec_clear_tx_fifo()
133 retry--; in hdmi_cec_clear_tx_fifo()
142 int temp; in hdmi_cec_clear_rx_fifo() local
144 hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3); in hdmi_cec_clear_rx_fifo()
147 temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL); in hdmi_cec_clear_rx_fifo()
148 if (FLD_GET(temp, 1, 0) == 0) in hdmi_cec_clear_rx_fifo()
150 retry--; in hdmi_cec_clear_rx_fifo()
158 int temp, err; in hdmi_cec_adap_enable() local
161 hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0); in hdmi_cec_adap_enable()
162 hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0); in hdmi_cec_adap_enable()
163 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); in hdmi_cec_adap_enable()
164 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
165 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
182 pr_err("cec-%s: could not clear TX FIFO\n", adap->name); in hdmi_cec_adap_enable()
183 err = -EIO; in hdmi_cec_adap_enable()
189 pr_err("cec-%s: could not clear RX FIFO\n", adap->name); in hdmi_cec_adap_enable()
190 err = -EIO; in hdmi_cec_adap_enable()
195 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, in hdmi_cec_adap_enable()
196 hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1)); in hdmi_cec_adap_enable()
197 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, in hdmi_cec_adap_enable()
198 hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0)); in hdmi_cec_adap_enable()
201 hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
203 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3); in hdmi_cec_adap_enable()
209 hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22); in hdmi_cec_adap_enable()
214 hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02); in hdmi_cec_adap_enable()
217 hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03); in hdmi_cec_adap_enable()
219 hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04); in hdmi_cec_adap_enable()
221 temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP); in hdmi_cec_adap_enable()
222 if (FLD_GET(temp, 4, 4) != 0) { in hdmi_cec_adap_enable()
223 temp = FLD_MOD(temp, 0, 4, 4); in hdmi_cec_adap_enable()
224 hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp); in hdmi_cec_adap_enable()
231 temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1); in hdmi_cec_adap_enable()
232 temp = FLD_MOD(0x0, 0x5, 2, 0); in hdmi_cec_adap_enable()
233 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
250 hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0); in hdmi_cec_adap_log_addr()
251 hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0); in hdmi_cec_adap_log_addr()
255 v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0); in hdmi_cec_adap_log_addr()
257 hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v); in hdmi_cec_adap_log_addr()
259 v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8); in hdmi_cec_adap_log_addr()
260 v |= 1 << (log_addr - 8); in hdmi_cec_adap_log_addr()
261 hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v); in hdmi_cec_adap_log_addr()
270 int temp; in hdmi_cec_adap_transmit() local
275 pr_err("cec-%s: could not clear TX FIFO for transmit\n", in hdmi_cec_adap_transmit()
276 adap->name); in hdmi_cec_adap_transmit()
277 return -EIO; in hdmi_cec_adap_transmit()
281 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, in hdmi_cec_adap_transmit()
284 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, in hdmi_cec_adap_transmit()
288 REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4); in hdmi_cec_adap_transmit()
291 hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg)); in hdmi_cec_adap_transmit()
294 temp = cec_msg_destination(msg); in hdmi_cec_adap_transmit()
295 if (msg->len == 1) in hdmi_cec_adap_transmit()
296 temp |= 0x80; in hdmi_cec_adap_transmit()
297 hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp); in hdmi_cec_adap_transmit()
298 if (msg->len == 1) in hdmi_cec_adap_transmit()
302 hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]); in hdmi_cec_adap_transmit()
304 for (i = 0; i < msg->len - 2; i++) in hdmi_cec_adap_transmit()
305 hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4, in hdmi_cec_adap_transmit()
306 msg->msg[2 + i]); in hdmi_cec_adap_transmit()
309 hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA, in hdmi_cec_adap_transmit()
310 (msg->len - 2) | 0x10); in hdmi_cec_adap_transmit()
322 cec_s_phys_addr(core->adap, pa, false); in hdmi4_cec_set_phys_addr()
332 core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core, in hdmi4_cec_init()
334 ret = PTR_ERR_OR_ZERO(core->adap); in hdmi4_cec_init()
337 core->wp = wp; in hdmi4_cec_init()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
342 ret = cec_register_adapter(core->adap, &pdev->dev); in hdmi4_cec_init()
344 cec_delete_adapter(core->adap); in hdmi4_cec_init()
352 cec_unregister_adapter(core->adap); in hdmi4_cec_uninit()