58 #define REG_FLD_MOD(dss, idx, val, start, end) \  macro
270 	REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */  in dss_sdi_enable()
274 	REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */  in dss_sdi_enable()
286 	REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28);  in dss_sdi_enable()
314 	REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */  in dss_sdi_enable()
328 	REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */  in dss_sdi_disable()
432 	REG_FLD_MOD(dss, DSS_CONTROL, b,		/* DISPC_CLK_SWITCH */  in dss_select_dispc_clk_source()
462 	REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos);	/* DSIx_CLK_SWITCH */  in dss_select_dsi_clk_source()
482 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_dra7()
490 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_dra7()
514 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap5()
521 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap5()
543 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap4()
550 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap4()
710 	REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);  in dss_set_venc_output()
716 	REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);  in dss_set_dac_pwrdn_bgz()
734 		REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);  in dss_select_hdmi_venc_clk_source()
762 	REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);  in dss_dpi_select_source_omap4()
789 	REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);  in dss_dpi_select_source_omap5()
1397 	REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);  in dss_probe_hardware()
1402 	REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4);	/* venc dac demen */  in dss_probe_hardware()
1403 	REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */  in dss_probe_hardware()
1404 	REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */  in dss_probe_hardware()