Lines Matching refs:DSSERR

168 		DSSERR("illegal DSS PLL ID %d\n", pll->id);  in dss_ctrl_pll_enable()
196 			DSSERR("error in PLL mux config for LCD\n");  in dss_ctrl_pll_set_control_mux()
212 			DSSERR("error in PLL mux config for LCD2\n");  in dss_ctrl_pll_set_control_mux()
228 			DSSERR("error in PLL mux config for LCD3\n");  in dss_ctrl_pll_set_control_mux()
234 		DSSERR("error in PLL mux config\n");  in dss_ctrl_pll_set_control_mux()
280 			DSSERR("PLL lock request timed out\n");  in dss_sdi_enable()
292 			DSSERR("PLL lock timed out\n");  in dss_sdi_enable()
303 			DSSERR("SDI reset timed out\n");  in dss_sdi_enable()
827 		DSSERR("can't get clock fck\n");  in dss_get_clocks()
836 			DSSERR("Failed to get %s\n",  in dss_get_clocks()
1269 			DSSERR("can't get DPLL VDDA regulator\n");  in dss_video_pll_probe()