Lines Matching +full:te +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-only
78 return dev_get_drvdata(dssdev->dev); in to_dsi_data()
92 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
93 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
94 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
106 case DSI_PROTO: base = dsi->proto_base; break; in dsi_read_reg()
107 case DSI_PHY: base = dsi->phy_base; break; in dsi_read_reg()
108 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
117 down(&dsi->bus_lock); in dsi_bus_lock()
122 up(&dsi->bus_lock); in dsi_bus_unlock()
127 return dsi->bus_lock.count == 0; in dsi_bus_is_locked()
145 while (t-- > 0) { in wait_for_bit_change()
167 dsi->perf_setup_time = ktime_get(); in dsi_perf_mark_setup()
172 dsi->perf_start_time = ktime_get(); in dsi_perf_mark_start()
186 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); in dsi_perf_show()
191 trans_time = ktime_sub(t, dsi->perf_start_time); in dsi_perf_show()
198 total_bytes = dsi->update_bytes; in dsi_perf_show()
320 spin_lock(&dsi->irq_stats_lock); in dsi_collect_irq_stats()
322 dsi->irq_stats.irq_count++; in dsi_collect_irq_stats()
323 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); in dsi_collect_irq_stats()
326 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); in dsi_collect_irq_stats()
328 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); in dsi_collect_irq_stats()
330 spin_unlock(&dsi->irq_stats_lock); in dsi_collect_irq_stats()
346 spin_lock(&dsi->errors_lock); in dsi_handle_irq_errors()
347 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; in dsi_handle_irq_errors()
348 spin_unlock(&dsi->errors_lock); in dsi_handle_irq_errors()
379 if (isr_data->isr && isr_data->mask & irqstatus) in dsi_call_isrs()
380 isr_data->isr(isr_data->arg, irqstatus); in dsi_call_isrs()
389 dsi_call_isrs(isr_tables->isr_table, in dsi_handle_isrs()
390 ARRAY_SIZE(isr_tables->isr_table), in dsi_handle_isrs()
396 dsi_call_isrs(isr_tables->isr_table_vc[i], in dsi_handle_isrs()
397 ARRAY_SIZE(isr_tables->isr_table_vc[i]), in dsi_handle_isrs()
402 dsi_call_isrs(isr_tables->isr_table_cio, in dsi_handle_isrs()
403 ARRAY_SIZE(isr_tables->isr_table_cio), in dsi_handle_isrs()
413 if (!dsi->is_enabled) in omap_dsi_irq_handler()
416 spin_lock(&dsi->irq_lock); in omap_dsi_irq_handler()
422 spin_unlock(&dsi->irq_lock); in omap_dsi_irq_handler()
455 del_timer(&dsi->te_timer); in omap_dsi_irq_handler()
460 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, in omap_dsi_irq_handler()
461 sizeof(dsi->isr_tables)); in omap_dsi_irq_handler()
463 spin_unlock(&dsi->irq_lock); in omap_dsi_irq_handler()
465 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); in omap_dsi_irq_handler()
474 /* dsi->irq_lock has to be locked by the caller */
492 if (isr_data->isr == NULL) in _omap_dsi_configure_irqs()
495 mask |= isr_data->mask; in _omap_dsi_configure_irqs()
508 /* dsi->irq_lock has to be locked by the caller */
515 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table, in _omap_dsi_set_irqs()
516 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, in _omap_dsi_set_irqs()
520 /* dsi->irq_lock has to be locked by the caller */
523 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc], in _omap_dsi_set_irqs_vc()
524 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), in _omap_dsi_set_irqs_vc()
529 /* dsi->irq_lock has to be locked by the caller */
532 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio, in _omap_dsi_set_irqs_cio()
533 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), in _omap_dsi_set_irqs_cio()
543 spin_lock_irqsave(&dsi->irq_lock, flags); in _dsi_initialize_irq()
545 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); in _dsi_initialize_irq()
552 spin_unlock_irqrestore(&dsi->irq_lock, flags); in _dsi_initialize_irq()
565 free_idx = -1; in _dsi_register_isr()
569 if (isr_data->isr == isr && isr_data->arg == arg && in _dsi_register_isr()
570 isr_data->mask == mask) { in _dsi_register_isr()
571 return -EINVAL; in _dsi_register_isr()
574 if (isr_data->isr == NULL && free_idx == -1) in _dsi_register_isr()
578 if (free_idx == -1) in _dsi_register_isr()
579 return -EBUSY; in _dsi_register_isr()
582 isr_data->isr = isr; in _dsi_register_isr()
583 isr_data->arg = arg; in _dsi_register_isr()
584 isr_data->mask = mask; in _dsi_register_isr()
597 if (isr_data->isr != isr || isr_data->arg != arg || in _dsi_unregister_isr()
598 isr_data->mask != mask) in _dsi_unregister_isr()
601 isr_data->isr = NULL; in _dsi_unregister_isr()
602 isr_data->arg = NULL; in _dsi_unregister_isr()
603 isr_data->mask = 0; in _dsi_unregister_isr()
608 return -EINVAL; in _dsi_unregister_isr()
617 spin_lock_irqsave(&dsi->irq_lock, flags); in dsi_register_isr()
619 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, in dsi_register_isr()
620 ARRAY_SIZE(dsi->isr_tables.isr_table)); in dsi_register_isr()
625 spin_unlock_irqrestore(&dsi->irq_lock, flags); in dsi_register_isr()
636 spin_lock_irqsave(&dsi->irq_lock, flags); in dsi_unregister_isr()
638 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, in dsi_unregister_isr()
639 ARRAY_SIZE(dsi->isr_tables.isr_table)); in dsi_unregister_isr()
644 spin_unlock_irqrestore(&dsi->irq_lock, flags); in dsi_unregister_isr()
655 spin_lock_irqsave(&dsi->irq_lock, flags); in dsi_register_isr_vc()
658 dsi->isr_tables.isr_table_vc[vc], in dsi_register_isr_vc()
659 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); in dsi_register_isr_vc()
664 spin_unlock_irqrestore(&dsi->irq_lock, flags); in dsi_register_isr_vc()
675 spin_lock_irqsave(&dsi->irq_lock, flags); in dsi_unregister_isr_vc()
678 dsi->isr_tables.isr_table_vc[vc], in dsi_unregister_isr_vc()
679 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); in dsi_unregister_isr_vc()
684 spin_unlock_irqrestore(&dsi->irq_lock, flags); in dsi_unregister_isr_vc()
694 spin_lock_irqsave(&dsi->errors_lock, flags); in dsi_get_errors()
695 e = dsi->errors; in dsi_get_errors()
696 dsi->errors = 0; in dsi_get_errors()
697 spin_unlock_irqrestore(&dsi->errors_lock, flags); in dsi_get_errors()
707 r = pm_runtime_get_sync(dsi->dev); in dsi_runtime_get()
709 pm_runtime_put_noidle(dsi->dev); in dsi_runtime_get()
721 r = pm_runtime_put_sync(dsi->dev); in dsi_runtime_put()
722 WARN_ON(r < 0 && r != -ENOSYS); in dsi_runtime_put()
734 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { in _dsi_print_reset_status()
769 return -EIO; in dsi_if_enable()
777 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; in dsi_get_pll_hsdiv_dispc_rate()
782 return dsi->pll.cinfo.clkout[HSDIV_DSI]; in dsi_get_pll_hsdiv_dsi_rate()
787 return dsi->pll.cinfo.clkdco / 16; in dsi_get_txbyteclkhs()
795 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id); in dsi_fclk_rate()
798 r = clk_get_rate(dsi->dss_clk); in dsi_fclk_rate()
818 return -EINVAL; in dsi_lp_clock_calc()
820 lp_cinfo->lp_clk_div = lp_clk_div; in dsi_lp_clock_calc()
821 lp_cinfo->lp_clk = lp_clk; in dsi_lp_clock_calc()
831 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv; in dsi_set_lp_clk_divisor()
834 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; in dsi_set_lp_clk_divisor()
837 return -EINVAL; in dsi_set_lp_clk_divisor()
844 dsi->current_lp_cinfo.lp_clk = lp_clk; in dsi_set_lp_clk_divisor()
845 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; in dsi_set_lp_clk_divisor()
858 if (dsi->scp_clk_refcount++ == 0) in dsi_enable_scp_clk()
864 WARN_ON(dsi->scp_clk_refcount == 0); in dsi_disable_scp_clk()
865 if (--dsi->scp_clk_refcount == 0) in dsi_disable_scp_clk()
880 /* DSI-PLL power command 0x3 is not working */ in dsi_pll_power()
881 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && in dsi_pll_power()
893 return -ENODEV; in dsi_pll_power()
907 max_dsi_fck = dsi->data->max_fck_freq; in dsi_pll_calc_dsi_fck()
909 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); in dsi_pll_calc_dsi_fck()
910 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; in dsi_pll_calc_dsi_fck()
929 r = regulator_enable(dsi->vdds_dsi_reg); in dsi_pll_enable()
934 dispc_pck_free_enable(dsi->dss->dispc, 1); in dsi_pll_enable()
938 r = -ENODEV; in dsi_pll_enable()
939 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable()
945 dispc_pck_free_enable(dsi->dss->dispc, 0); in dsi_pll_enable()
956 regulator_disable(dsi->vdds_dsi_reg); in dsi_pll_enable()
969 regulator_disable(dsi->vdds_dsi_reg); in dsi_pll_disable()
979 struct dsi_data *dsi = s->private; in dsi_dump_dsi_clocks()
980 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; in dsi_dump_dsi_clocks()
982 int dsi_module = dsi->module_id; in dsi_dump_dsi_clocks()
983 struct dss_pll *pll = &dsi->pll; in dsi_dump_dsi_clocks()
985 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss); in dsi_dump_dsi_clocks()
986 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module); in dsi_dump_dsi_clocks()
991 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); in dsi_dump_dsi_clocks()
993 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); in dsi_dump_dsi_clocks()
995 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); in dsi_dump_dsi_clocks()
997 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", in dsi_dump_dsi_clocks()
998 cinfo->clkdco, cinfo->m); in dsi_dump_dsi_clocks()
1000 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", in dsi_dump_dsi_clocks()
1004 cinfo->clkout[HSDIV_DISPC], in dsi_dump_dsi_clocks()
1005 cinfo->mX[HSDIV_DISPC], in dsi_dump_dsi_clocks()
1009 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", in dsi_dump_dsi_clocks()
1013 cinfo->clkout[HSDIV_DSI], in dsi_dump_dsi_clocks()
1014 cinfo->mX[HSDIV_DSI], in dsi_dump_dsi_clocks()
1018 seq_printf(s, "- DSI%d -\n", dsi_module + 1); in dsi_dump_dsi_clocks()
1026 cinfo->clkdco / 4); in dsi_dump_dsi_clocks()
1030 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); in dsi_dump_dsi_clocks()
1040 struct dsi_data *dsi = s->private; in dsi_dump_dsi_irqs()
1046 return -ENOMEM; in dsi_dump_dsi_irqs()
1048 spin_lock_irqsave(&dsi->irq_stats_lock, flags); in dsi_dump_dsi_irqs()
1050 *stats = dsi->irq_stats; in dsi_dump_dsi_irqs()
1051 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); in dsi_dump_dsi_irqs()
1052 dsi->irq_stats.last_reset = jiffies; in dsi_dump_dsi_irqs()
1054 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); in dsi_dump_dsi_irqs()
1057 jiffies_to_msecs(jiffies - stats->last_reset)); in dsi_dump_dsi_irqs()
1059 seq_printf(s, "irqs %d\n", stats->irq_count); in dsi_dump_dsi_irqs()
1061 seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1]); in dsi_dump_dsi_irqs()
1063 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); in dsi_dump_dsi_irqs()
1084 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ in dsi_dump_dsi_irqs()
1085 stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ in dsi_dump_dsi_irqs()
1086 stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ in dsi_dump_dsi_irqs()
1087 stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ in dsi_dump_dsi_irqs()
1088 stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); in dsi_dump_dsi_irqs()
1090 seq_printf(s, "-- VC interrupts --\n"); in dsi_dump_dsi_irqs()
1103 seq_printf(s, "%-20s %10d\n", #x, \ in dsi_dump_dsi_irqs()
1104 stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); in dsi_dump_dsi_irqs()
1106 seq_printf(s, "-- CIO interrupts --\n"); in dsi_dump_dsi_irqs()
1137 struct dsi_data *dsi = s->private; in dsi_dump_dsi_regs()
1143 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) in dsi_dump_dsi_regs()
1240 return -ENODEV; in dsi_cio_power()
1256 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) in dsi_get_line_buf_size()
1297 for (i = 0; i < dsi->num_lanes_used; ++i) { in dsi_set_lane_config()
1302 for (t = 0; t < dsi->num_lanes_supported; ++t) in dsi_set_lane_config()
1303 if (dsi->lanes[t].function == functions[i]) in dsi_set_lane_config()
1306 if (t == dsi->num_lanes_supported) in dsi_set_lane_config()
1307 return -EINVAL; in dsi_set_lane_config()
1310 polarity = dsi->lanes[t].polarity; in dsi_set_lane_config()
1317 for (; i < dsi->num_lanes_supported; ++i) { in dsi_set_lane_config()
1332 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; in ns2ddr()
1339 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; in ddr2ns()
1376 /* min tclk-prepare + tclk-zero = 300ns */ in dsi_cio_timings()
1408 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { in dsi_cio_timings()
1429 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) in dsi_cio_wait_tx_clk_esc_reset()
1434 for (i = 0; i < dsi->num_lanes_supported; ++i) in dsi_cio_wait_tx_clk_esc_reset()
1435 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; in dsi_cio_wait_tx_clk_esc_reset()
1445 for (i = 0; i < dsi->num_lanes_supported; ++i) { in dsi_cio_wait_tx_clk_esc_reset()
1450 if (ok == dsi->num_lanes_supported) in dsi_cio_wait_tx_clk_esc_reset()
1453 if (--t == 0) { in dsi_cio_wait_tx_clk_esc_reset()
1454 for (i = 0; i < dsi->num_lanes_supported; ++i) { in dsi_cio_wait_tx_clk_esc_reset()
1461 return -EIO; in dsi_cio_wait_tx_clk_esc_reset()
1474 for (i = 0; i < dsi->num_lanes_supported; ++i) { in dsi_get_lane_mask()
1475 if (dsi->lanes[i].function != DSI_LANE_UNUSED) in dsi_get_lane_mask()
1499 if (dsi->module_id == 0) { in dsi_omap4_mux_pads()
1504 } else if (dsi->module_id == 1) { in dsi_omap4_mux_pads()
1510 return -ENODEV; in dsi_omap4_mux_pads()
1513 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, in dsi_omap4_mux_pads()
1530 if (dsi->module_id == 0) in dsi_omap5_mux_pads()
1532 else if (dsi->module_id == 1) in dsi_omap5_mux_pads()
1535 return -ENODEV; in dsi_omap5_mux_pads()
1537 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, in dsi_omap5_mux_pads()
1544 if (dsi->data->model == DSI_MODEL_OMAP4) in dsi_enable_pads()
1546 if (dsi->data->model == DSI_MODEL_OMAP5) in dsi_enable_pads()
1553 if (dsi->data->model == DSI_MODEL_OMAP4) in dsi_disable_pads()
1555 else if (dsi->data->model == DSI_MODEL_OMAP5) in dsi_disable_pads()
1579 r = -EIO; in dsi_cio_init()
1601 r = -ENODEV; in dsi_cio_init()
1620 !(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS), in dsi_cio_init()
1656 dsi->vc[0].tx_fifo_size = size1; in dsi_config_tx_fifo()
1657 dsi->vc[1].tx_fifo_size = size2; in dsi_config_tx_fifo()
1658 dsi->vc[2].tx_fifo_size = size3; in dsi_config_tx_fifo()
1659 dsi->vc[3].tx_fifo_size = size4; in dsi_config_tx_fifo()
1663 int size = dsi->vc[i].tx_fifo_size; in dsi_config_tx_fifo()
1688 dsi->vc[0].rx_fifo_size = size1; in dsi_config_rx_fifo()
1689 dsi->vc[1].rx_fifo_size = size2; in dsi_config_rx_fifo()
1690 dsi->vc[2].rx_fifo_size = size3; in dsi_config_rx_fifo()
1691 dsi->vc[3].rx_fifo_size = size4; in dsi_config_rx_fifo()
1695 int size = dsi->vc[i].rx_fifo_size; in dsi_config_rx_fifo()
1722 return -EIO; in dsi_force_tx_stop_mode_io()
1737 struct dsi_data *dsi = vp_data->dsi; in dsi_packet_sent_handler_vp()
1738 const int vc = dsi->update_vc; in dsi_packet_sent_handler_vp()
1739 u8 bit = dsi->te_enabled ? 30 : 31; in dsi_packet_sent_handler_vp()
1742 complete(vp_data->completion); in dsi_packet_sent_handler_vp()
1755 bit = dsi->te_enabled ? 30 : 31; in dsi_sync_vc_vp()
1767 r = -EIO; in dsi_sync_vc_vp()
1787 struct dsi_data *dsi = l4_data->dsi; in dsi_packet_sent_handler_l4()
1788 const int vc = dsi->update_vc; in dsi_packet_sent_handler_l4()
1791 complete(l4_data->completion); in dsi_packet_sent_handler_l4()
1813 r = -EIO; in dsi_sync_vc_l4()
1838 switch (dsi->vc[vc].source) { in dsi_sync_vc()
1845 return -EINVAL; in dsi_sync_vc()
1860 return -EIO; in dsi_vc_enable()
1885 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) in dsi_vc_initial_config()
1893 dsi->vc[vc].source = DSI_VC_SOURCE_L4; in dsi_vc_initial_config()
1952 DSSERR("\t\tECC Error, single-bit (corrected)\n"); in dsi_show_rx_ack_with_err()
1954 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); in dsi_show_rx_ack_with_err()
2000 if (dsi->debug_write || dsi->debug_read) in dsi_vc_send_bta()
2043 r = -EIO; in dsi_vc_send_bta_sync()
2050 r = -EIO; in dsi_vc_send_bta_sync()
2102 if (dsi->debug_write) in dsi_vc_send_long()
2103 DSSDBG("dsi_vc_send_long, %zu bytes\n", msg->tx_len); in dsi_vc_send_long()
2106 if (dsi->vc[vc].tx_fifo_size * 32 * 4 < msg->tx_len + 4) { in dsi_vc_send_long()
2108 return -EINVAL; in dsi_vc_send_long()
2111 dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0); in dsi_vc_send_long()
2113 p = msg->tx_buf; in dsi_vc_send_long()
2114 for (i = 0; i < msg->tx_len >> 2; i++) { in dsi_vc_send_long()
2115 if (dsi->debug_write) in dsi_vc_send_long()
2126 i = msg->tx_len % 4; in dsi_vc_send_long()
2130 if (dsi->debug_write) in dsi_vc_send_long()
2167 if (dsi->debug_write) in dsi_vc_send_short()
2169 vc, msg->type, pkt.header[1], pkt.header[2]); in dsi_vc_send_short()
2173 return -EINVAL; in dsi_vc_send_short()
2200 if (mipi_dsi_packet_format_is_short(msg->type)) in dsi_vc_write_common()
2225 return -EIO; in dsi_vc_write_common()
2241 r = -EIO; in dsi_vc_read_rx_fifo()
2246 if (dsi->debug_read) in dsi_vc_read_rx_fifo()
2252 r = -EIO; in dsi_vc_read_rx_fifo()
2259 if (dsi->debug_read) in dsi_vc_read_rx_fifo()
2265 r = -EIO; in dsi_vc_read_rx_fifo()
2276 if (dsi->debug_read) in dsi_vc_read_rx_fifo()
2282 r = -EIO; in dsi_vc_read_rx_fifo()
2295 if (dsi->debug_read) in dsi_vc_read_rx_fifo()
2301 r = -EIO; in dsi_vc_read_rx_fifo()
2310 if (dsi->debug_read) in dsi_vc_read_rx_fifo()
2328 r = -EIO; in dsi_vc_read_rx_fifo()
2343 u8 cmd = ((u8 *)msg->tx_buf)[0]; in dsi_vc_dcs_read()
2346 if (dsi->debug_read) in dsi_vc_dcs_read()
2357 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, in dsi_vc_dcs_read()
2362 if (r != msg->rx_len) { in dsi_vc_dcs_read()
2363 r = -EIO; in dsi_vc_dcs_read()
2387 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, in dsi_vc_generic_read()
2392 if (r != msg->rx_len) { in dsi_vc_generic_read()
2393 r = -EIO; in dsi_vc_generic_read()
2399 DSSERR("%s(vc %d, reqlen %zu) failed\n", __func__, vc, msg->tx_len); in dsi_vc_generic_read()
2515 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { in dsi_config_vp_num_line_buffers()
2516 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); in dsi_config_vp_num_line_buffers()
2517 const struct videomode *vm = &dsi->vm; in dsi_config_vp_num_line_buffers()
2522 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) in dsi_config_vp_num_line_buffers()
2540 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) in dsi_config_vp_sync_events()
2558 int blanking_mode = dsi->vm_timings.blanking_mode; in dsi_config_blanking_modes()
2559 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; in dsi_config_blanking_modes()
2560 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; in dsi_config_blanking_modes()
2561 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; in dsi_config_blanking_modes()
2605 return blank > transition ? blank - transition : 0; in dsi_compute_interleave_hs()
2628 tlp_avail = thsbyte_clk * (blank - trans_lp); in dsi_compute_interleave_lp()
2632 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - in dsi_compute_interleave_lp()
2646 const struct videomode *vm = &dsi->vm; in dsi_config_cmd_mode_interleaving()
2647 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); in dsi_config_cmd_mode_interleaving()
2648 int ndl = dsi->num_lanes_used - 1; in dsi_config_cmd_mode_interleaving()
2649 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; in dsi_config_cmd_mode_interleaving()
2687 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); in dsi_config_cmd_mode_interleaving()
2775 switch (mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt)) { in dsi_proto_config()
2787 return -EINVAL; in dsi_proto_config()
2799 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { in dsi_proto_config()
2809 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { in dsi_proto_config()
2832 int ndl = dsi->num_lanes_used - 1; in dsi_proto_timings()
2838 ths_zero = ths_prepare_ths_zero - ths_prepare; in dsi_proto_timings()
2885 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { in dsi_proto_timings()
2887 int hsa = dsi->vm_timings.hsa; in dsi_proto_timings()
2888 int hfp = dsi->vm_timings.hfp; in dsi_proto_timings()
2889 int hbp = dsi->vm_timings.hbp; in dsi_proto_timings()
2890 int vsa = dsi->vm_timings.vsa; in dsi_proto_timings()
2891 int vfp = dsi->vm_timings.vfp; in dsi_proto_timings()
2892 int vbp = dsi->vm_timings.vbp; in dsi_proto_timings()
2893 int window_sync = dsi->vm_timings.window_sync; in dsi_proto_timings()
2895 const struct videomode *vm = &dsi->vm; in dsi_proto_timings()
2896 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); in dsi_proto_timings()
2899 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; in dsi_proto_timings()
2903 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); in dsi_proto_timings()
2912 vsa, vm->vactive); in dsi_proto_timings()
2928 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ in dsi_proto_timings()
2949 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 in dsi_configure_pins()
2951 return -EINVAL; in dsi_configure_pins()
2965 if (dx >= dsi->num_lanes_supported * 2) in dsi_configure_pins()
2966 return -EINVAL; in dsi_configure_pins()
2968 if (dy >= dsi->num_lanes_supported * 2) in dsi_configure_pins()
2969 return -EINVAL; in dsi_configure_pins()
2972 if (dy != dx - 1) in dsi_configure_pins()
2973 return -EINVAL; in dsi_configure_pins()
2977 return -EINVAL; in dsi_configure_pins()
2988 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); in dsi_configure_pins()
2989 dsi->num_lanes_used = num_lanes; in dsi_configure_pins()
2996 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); in dsi_enable_video_mode()
3000 switch (dsi->pix_fmt) { in dsi_enable_video_mode()
3014 return -EINVAL; in dsi_enable_video_mode()
3023 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); in dsi_enable_video_mode()
3025 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, data_type, in dsi_enable_video_mode()
3053 dev_err(dsi->dev, "failed to init dispc!\n"); in dsi_enable_video_output()
3057 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { in dsi_enable_video_output()
3063 r = dss_mgr_enable(&dsi->output); in dsi_enable_video_output()
3070 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { in dsi_enable_video_output()
3076 dev_err(dsi->dev, "failed to enable DSI encoder!\n"); in dsi_enable_video_output()
3084 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) in dsi_disable_video_output()
3087 dss_mgr_disable(&dsi->output); in dsi_disable_video_output()
3102 const unsigned vc = dsi->update_vc; in dsi_update_screen_dispc()
3103 const unsigned int line_buf_size = dsi->line_buffer_size; in dsi_update_screen_dispc()
3104 u16 w = dsi->vm.hactive; in dsi_update_screen_dispc()
3105 u16 h = dsi->vm.vactive; in dsi_update_screen_dispc()
3109 bytespp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; in dsi_update_screen_dispc()
3130 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, MIPI_DSI_DCS_LONG_WRITE, in dsi_update_screen_dispc()
3133 if (dsi->te_enabled) in dsi_update_screen_dispc()
3139 /* We put SIDLEMODE to no-idle for the duration of the transfer, in dsi_update_screen_dispc()
3145 dispc_disable_sidle(dsi->dss->dispc); in dsi_update_screen_dispc()
3149 r = schedule_delayed_work(&dsi->framedone_timeout_work, in dsi_update_screen_dispc()
3153 dss_mgr_start_update(&dsi->output); in dsi_update_screen_dispc()
3155 if (dsi->te_enabled) { in dsi_update_screen_dispc()
3156 /* disable LP_RX_TO, so that we can receive TE. Time to wait in dsi_update_screen_dispc()
3157 * for TE is longer than the timer allows */ in dsi_update_screen_dispc()
3163 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); in dsi_update_screen_dispc()
3171 DSSERR("TE not received for 250ms!\n"); in dsi_te_timeout()
3177 /* SIDLEMODE back to smart-idle */ in dsi_handle_framedone()
3178 dispc_enable_sidle(dsi->dss->dispc); in dsi_handle_framedone()
3180 if (dsi->te_enabled) { in dsi_handle_framedone()
3181 /* enable LP_RX_TO again after the TE */ in dsi_handle_framedone()
3204 dsi_handle_framedone(dsi, -ETIMEDOUT); in dsi_framedone_timeout_work_callback()
3216 cancel_delayed_work(&dsi->framedone_timeout_work); in dsi_framedone_irq_callback()
3228 dsi->update_bytes = dsi->vm.hactive * dsi->vm.vactive * in _dsi_update()
3229 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; in _dsi_update()
3258 if (!dsi->video_enabled) { in dsi_update_channel()
3259 r = -EIO; in dsi_update_channel()
3263 if (dsi->vm.hactive == 0 || dsi->vm.vactive == 0) { in dsi_update_channel()
3264 r = -EINVAL; in dsi_update_channel()
3275 r = _dsi_send_nop(dsi, VC_CMD, dsi->dsidev->channel); in dsi_update_channel()
3281 dsi->update_vc = vc; in dsi_update_channel()
3283 if (dsi->te_enabled && dsi->te_gpio) { in dsi_update_channel()
3284 schedule_delayed_work(&dsi->te_timeout_work, in dsi_update_channel()
3286 atomic_set(&dsi->do_ext_te_update, 1); in dsi_update_channel()
3313 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; in dsi_configure_dispc_clocks()
3314 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; in dsi_configure_dispc_clocks()
3316 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); in dsi_configure_dispc_clocks()
3322 dsi->mgr_config.clock_info = dispc_cinfo; in dsi_configure_dispc_clocks()
3329 enum omap_channel dispc_channel = dsi->output.dispc_channel; in dsi_init_dispc()
3332 dss_select_lcd_clk_source(dsi->dss, dispc_channel, dsi->module_id == 0 ? in dsi_init_dispc()
3336 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { in dsi_init_dispc()
3337 r = dss_mgr_register_framedone_handler(&dsi->output, in dsi_init_dispc()
3344 dsi->mgr_config.stallmode = true; in dsi_init_dispc()
3345 dsi->mgr_config.fifohandcheck = true; in dsi_init_dispc()
3347 dsi->mgr_config.stallmode = false; in dsi_init_dispc()
3348 dsi->mgr_config.fifohandcheck = false; in dsi_init_dispc()
3355 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; in dsi_init_dispc()
3356 dsi->mgr_config.video_port_width = in dsi_init_dispc()
3357 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); in dsi_init_dispc()
3358 dsi->mgr_config.lcden_sig_polarity = 0; in dsi_init_dispc()
3360 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config); in dsi_init_dispc()
3364 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) in dsi_init_dispc()
3365 dss_mgr_unregister_framedone_handler(&dsi->output, in dsi_init_dispc()
3368 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); in dsi_init_dispc()
3374 enum omap_channel dispc_channel = dsi->output.dispc_channel; in dsi_uninit_dispc()
3376 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) in dsi_uninit_dispc()
3377 dss_mgr_unregister_framedone_handler(&dsi->output, in dsi_uninit_dispc()
3380 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); in dsi_uninit_dispc()
3388 cinfo = dsi->user_dsi_cinfo; in dsi_configure_dsi_clocks()
3390 r = dss_pll_set_config(&dsi->pll, &cinfo); in dsi_configure_dsi_clocks()
3405 dsi->vc[VC_CMD].source = DSI_VC_SOURCE_L4; in dsi_setup_dsi_vcs()
3411 dsi->vc[VC_VIDEO].source = DSI_VC_SOURCE_VP; in dsi_setup_dsi_vcs()
3413 if ((dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) && in dsi_setup_dsi_vcs()
3414 !(dsi->dsidev->mode_flags & MIPI_DSI_MODE_VIDEO)) in dsi_setup_dsi_vcs()
3425 if (!(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) in dsi_setup_dsi_vcs()
3426 dsi_vc_send_null(dsi, VC_CMD, dsi->dsidev->channel); in dsi_setup_dsi_vcs()
3433 r = dss_pll_enable(&dsi->pll); in dsi_init_dsi()
3441 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, in dsi_init_dsi()
3442 dsi->module_id == 0 ? in dsi_init_dsi()
3447 if (!dsi->vdds_dsi_enabled) { in dsi_init_dsi()
3448 r = regulator_enable(dsi->vdds_dsi_reg); in dsi_init_dsi()
3452 dsi->vdds_dsi_enabled = true; in dsi_init_dsi()
3477 regulator_disable(dsi->vdds_dsi_reg); in dsi_init_dsi()
3478 dsi->vdds_dsi_enabled = false; in dsi_init_dsi()
3480 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); in dsi_init_dsi()
3482 dss_pll_disable(&dsi->pll); in dsi_init_dsi()
3496 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); in dsi_uninit_dsi()
3498 dss_pll_disable(&dsi->pll); in dsi_uninit_dsi()
3500 regulator_disable(dsi->vdds_dsi_reg); in dsi_uninit_dsi()
3501 dsi->vdds_dsi_enabled = false; in dsi_uninit_dsi()
3510 if (WARN_ON(dsi->iface_enabled)) in dsi_enable()
3513 mutex_lock(&dsi->lock); in dsi_enable()
3525 dsi->iface_enabled = true; in dsi_enable()
3527 mutex_unlock(&dsi->lock); in dsi_enable()
3534 mutex_unlock(&dsi->lock); in dsi_enable()
3542 if (WARN_ON(!dsi->iface_enabled)) in dsi_disable()
3545 mutex_lock(&dsi->lock); in dsi_disable()
3556 dsi->iface_enabled = false; in dsi_disable()
3558 mutex_unlock(&dsi->lock); in dsi_disable()
3563 dsi->te_enabled = enable; in dsi_enable_te()
3565 if (dsi->te_gpio) { in dsi_enable_te()
3567 enable_irq(dsi->te_irq); in dsi_enable_te()
3569 disable_irq(dsi->te_irq); in dsi_enable_te()
3579 unsigned long byteclk = t->hsclk / 4; in print_dsi_vm()
3582 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); in print_dsi_vm()
3583 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ in print_dsi_vm()
3584 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; in print_dsi_vm()
3593 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, in print_dsi_vm()
3595 TO_DSI_T(t->hss), in print_dsi_vm()
3596 TO_DSI_T(t->hsa), in print_dsi_vm()
3597 TO_DSI_T(t->hse), in print_dsi_vm()
3598 TO_DSI_T(t->hbp), in print_dsi_vm()
3600 TO_DSI_T(t->hfp), in print_dsi_vm()
3611 unsigned long pck = vm->pixelclock; in print_dispc_vm()
3614 hact = vm->hactive; in print_dispc_vm()
3615 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; in print_dispc_vm()
3624 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, in print_dispc_vm()
3626 TO_DISPC_T(vm->hsync_len), in print_dispc_vm()
3627 TO_DISPC_T(vm->hback_porch), in print_dispc_vm()
3629 TO_DISPC_T(vm->hfront_porch), in print_dispc_vm()
3641 unsigned long byteclk = t->hsclk / 4; in print_dsi_dispc_vm()
3646 dsi_tput = (u64)byteclk * t->ndl * 8; in print_dsi_dispc_vm()
3647 pck = (u32)div64_u64(dsi_tput, t->bitspp); in print_dsi_dispc_vm()
3648 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); in print_dsi_dispc_vm()
3649 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; in print_dsi_dispc_vm()
3652 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); in print_dsi_dispc_vm()
3653 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); in print_dsi_dispc_vm()
3654 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); in print_dsi_dispc_vm()
3655 vm.hactive = t->hact; in print_dsi_dispc_vm()
3665 struct videomode *vm = &ctx->vm; in dsi_cm_calc_dispc_cb()
3667 ctx->dispc_cinfo.lck_div = lckd; in dsi_cm_calc_dispc_cb()
3668 ctx->dispc_cinfo.pck_div = pckd; in dsi_cm_calc_dispc_cb()
3669 ctx->dispc_cinfo.lck = lck; in dsi_cm_calc_dispc_cb()
3670 ctx->dispc_cinfo.pck = pck; in dsi_cm_calc_dispc_cb()
3672 *vm = *ctx->config->vm; in dsi_cm_calc_dispc_cb()
3673 vm->pixelclock = pck; in dsi_cm_calc_dispc_cb()
3674 vm->hactive = ctx->config->vm->hactive; in dsi_cm_calc_dispc_cb()
3675 vm->vactive = ctx->config->vm->vactive; in dsi_cm_calc_dispc_cb()
3676 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; in dsi_cm_calc_dispc_cb()
3677 vm->vfront_porch = vm->vback_porch = 0; in dsi_cm_calc_dispc_cb()
3687 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dsi_cm_calc_hsdiv_cb()
3688 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dsi_cm_calc_hsdiv_cb()
3690 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, in dsi_cm_calc_hsdiv_cb()
3691 ctx->req_pck_min, ctx->req_pck_max, in dsi_cm_calc_hsdiv_cb()
3699 struct dsi_data *dsi = ctx->dsi; in dsi_cm_calc_pll_cb()
3701 ctx->dsi_cinfo.n = n; in dsi_cm_calc_pll_cb()
3702 ctx->dsi_cinfo.m = m; in dsi_cm_calc_pll_cb()
3703 ctx->dsi_cinfo.fint = fint; in dsi_cm_calc_pll_cb()
3704 ctx->dsi_cinfo.clkdco = clkdco; in dsi_cm_calc_pll_cb()
3706 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, in dsi_cm_calc_pll_cb()
3707 dsi->data->max_fck_freq, in dsi_cm_calc_pll_cb()
3720 clkin = clk_get_rate(dsi->pll.clkin); in dsi_cm_calc()
3721 bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); in dsi_cm_calc()
3722 ndl = dsi->num_lanes_used - 1; in dsi_cm_calc()
3726 * frame in time, and also to handle TE. That's not very simple, though, in dsi_cm_calc()
3730 pck = cfg->vm->pixelclock; in dsi_cm_calc()
3735 ctx->dsi = dsi; in dsi_cm_calc()
3736 ctx->pll = &dsi->pll; in dsi_cm_calc()
3737 ctx->config = cfg; in dsi_cm_calc()
3738 ctx->req_pck_min = pck; in dsi_cm_calc()
3739 ctx->req_pck_nom = pck; in dsi_cm_calc()
3740 ctx->req_pck_max = pck * 3 / 2; in dsi_cm_calc()
3742 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); in dsi_cm_calc()
3743 pll_max = cfg->hs_clk_max * 4; in dsi_cm_calc()
3745 return dss_pll_calc_a(ctx->pll, clkin, in dsi_cm_calc()
3752 struct dsi_data *dsi = ctx->dsi; in dsi_vm_calc_blanking()
3753 const struct omap_dss_dsi_config *cfg = ctx->config; in dsi_vm_calc_blanking()
3754 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); in dsi_vm_calc_blanking()
3755 int ndl = dsi->num_lanes_used - 1; in dsi_vm_calc_blanking()
3756 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; in dsi_vm_calc_blanking()
3772 req_vm = cfg->vm; in dsi_vm_calc_blanking()
3773 req_pck_min = ctx->req_pck_min; in dsi_vm_calc_blanking()
3774 req_pck_max = ctx->req_pck_max; in dsi_vm_calc_blanking()
3775 req_pck_nom = ctx->req_pck_nom; in dsi_vm_calc_blanking()
3777 dispc_pck = ctx->dispc_cinfo.pck; in dsi_vm_calc_blanking()
3780 xres = req_vm->hactive; in dsi_vm_calc_blanking()
3782 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + in dsi_vm_calc_blanking()
3783 req_vm->hsync_len; in dsi_vm_calc_blanking()
3792 if (dsi->line_buffer_size < xres * bitspp / 8) { in dsi_vm_calc_blanking()
3804 /* When non-burst mode, DSI tput must be below max requirement. */ in dsi_vm_calc_blanking()
3805 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { in dsi_vm_calc_blanking()
3812 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { in dsi_vm_calc_blanking()
3813 if (ndl == 3 && req_vm->hsync_len == 0) in dsi_vm_calc_blanking()
3829 dsi_hbl = dsi_htot - dsi_hact; in dsi_vm_calc_blanking()
3838 dispc_hbl = dispc_htot - xres; in dsi_vm_calc_blanking()
3842 dsi_vm = &ctx->dsi_vm; in dsi_vm_calc_blanking()
3845 dsi_vm->hsclk = hsclk; in dsi_vm_calc_blanking()
3847 dsi_vm->ndl = ndl; in dsi_vm_calc_blanking()
3848 dsi_vm->bitspp = bitspp; in dsi_vm_calc_blanking()
3850 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { in dsi_vm_calc_blanking()
3852 } else if (ndl == 3 && req_vm->hsync_len == 0) { in dsi_vm_calc_blanking()
3855 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); in dsi_vm_calc_blanking()
3856 hsa = max(hsa - hse, 1); in dsi_vm_calc_blanking()
3859 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); in dsi_vm_calc_blanking()
3862 hfp = dsi_hbl - (hss + hsa + hse + hbp); in dsi_vm_calc_blanking()
3867 t = 1 - hfp; in dsi_vm_calc_blanking()
3868 hbp = max(hbp - t, 1); in dsi_vm_calc_blanking()
3869 hfp = dsi_hbl - (hss + hsa + hse + hbp); in dsi_vm_calc_blanking()
3873 t = 1 - hfp; in dsi_vm_calc_blanking()
3874 hsa = max(hsa - t, 1); in dsi_vm_calc_blanking()
3875 hfp = dsi_hbl - (hss + hsa + hse + hbp); in dsi_vm_calc_blanking()
3882 dsi_vm->hss = hss; in dsi_vm_calc_blanking()
3883 dsi_vm->hsa = hsa; in dsi_vm_calc_blanking()
3884 dsi_vm->hse = hse; in dsi_vm_calc_blanking()
3885 dsi_vm->hbp = hbp; in dsi_vm_calc_blanking()
3886 dsi_vm->hact = xres; in dsi_vm_calc_blanking()
3887 dsi_vm->hfp = hfp; in dsi_vm_calc_blanking()
3889 dsi_vm->vsa = req_vm->vsync_len; in dsi_vm_calc_blanking()
3890 dsi_vm->vbp = req_vm->vback_porch; in dsi_vm_calc_blanking()
3891 dsi_vm->vact = req_vm->vactive; in dsi_vm_calc_blanking()
3892 dsi_vm->vfp = req_vm->vfront_porch; in dsi_vm_calc_blanking()
3894 dsi_vm->trans_mode = cfg->trans_mode; in dsi_vm_calc_blanking()
3896 dsi_vm->blanking_mode = 0; in dsi_vm_calc_blanking()
3897 dsi_vm->hsa_blanking_mode = 1; in dsi_vm_calc_blanking()
3898 dsi_vm->hfp_blanking_mode = 1; in dsi_vm_calc_blanking()
3899 dsi_vm->hbp_blanking_mode = 1; in dsi_vm_calc_blanking()
3901 dsi_vm->window_sync = 4; in dsi_vm_calc_blanking()
3905 dispc_vm = &ctx->vm; in dsi_vm_calc_blanking()
3907 dispc_vm->pixelclock = dispc_pck; in dsi_vm_calc_blanking()
3909 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { in dsi_vm_calc_blanking()
3910 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, in dsi_vm_calc_blanking()
3917 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); in dsi_vm_calc_blanking()
3920 hfp = dispc_hbl - hsa - hbp; in dsi_vm_calc_blanking()
3925 t = 1 - hfp; in dsi_vm_calc_blanking()
3926 hbp = max(hbp - t, 1); in dsi_vm_calc_blanking()
3927 hfp = dispc_hbl - hsa - hbp; in dsi_vm_calc_blanking()
3931 t = 1 - hfp; in dsi_vm_calc_blanking()
3932 hsa = max(hsa - t, 1); in dsi_vm_calc_blanking()
3933 hfp = dispc_hbl - hsa - hbp; in dsi_vm_calc_blanking()
3940 dispc_vm->hfront_porch = hfp; in dsi_vm_calc_blanking()
3941 dispc_vm->hsync_len = hsa; in dsi_vm_calc_blanking()
3942 dispc_vm->hback_porch = hbp; in dsi_vm_calc_blanking()
3953 ctx->dispc_cinfo.lck_div = lckd; in dsi_vm_calc_dispc_cb()
3954 ctx->dispc_cinfo.pck_div = pckd; in dsi_vm_calc_dispc_cb()
3955 ctx->dispc_cinfo.lck = lck; in dsi_vm_calc_dispc_cb()
3956 ctx->dispc_cinfo.pck = pck; in dsi_vm_calc_dispc_cb()
3962 print_dispc_vm("dispc", &ctx->vm); in dsi_vm_calc_dispc_cb()
3963 print_dsi_vm("dsi ", &ctx->dsi_vm); in dsi_vm_calc_dispc_cb()
3964 print_dispc_vm("req ", ctx->config->vm); in dsi_vm_calc_dispc_cb()
3965 print_dsi_dispc_vm("act ", &ctx->dsi_vm); in dsi_vm_calc_dispc_cb()
3977 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dsi_vm_calc_hsdiv_cb()
3978 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; in dsi_vm_calc_hsdiv_cb()
3985 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) in dsi_vm_calc_hsdiv_cb()
3986 pck_max = ctx->req_pck_max + 10000000; in dsi_vm_calc_hsdiv_cb()
3988 pck_max = ctx->req_pck_max; in dsi_vm_calc_hsdiv_cb()
3990 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, in dsi_vm_calc_hsdiv_cb()
3991 ctx->req_pck_min, pck_max, in dsi_vm_calc_hsdiv_cb()
3999 struct dsi_data *dsi = ctx->dsi; in dsi_vm_calc_pll_cb()
4001 ctx->dsi_cinfo.n = n; in dsi_vm_calc_pll_cb()
4002 ctx->dsi_cinfo.m = m; in dsi_vm_calc_pll_cb()
4003 ctx->dsi_cinfo.fint = fint; in dsi_vm_calc_pll_cb()
4004 ctx->dsi_cinfo.clkdco = clkdco; in dsi_vm_calc_pll_cb()
4006 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, in dsi_vm_calc_pll_cb()
4007 dsi->data->max_fck_freq, in dsi_vm_calc_pll_cb()
4015 const struct videomode *vm = cfg->vm; in dsi_vm_calc()
4019 int ndl = dsi->num_lanes_used - 1; in dsi_vm_calc()
4020 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); in dsi_vm_calc()
4023 clkin = clk_get_rate(dsi->pll.clkin); in dsi_vm_calc()
4026 ctx->dsi = dsi; in dsi_vm_calc()
4027 ctx->pll = &dsi->pll; in dsi_vm_calc()
4028 ctx->config = cfg; in dsi_vm_calc()
4031 ctx->req_pck_min = vm->pixelclock - 1000; in dsi_vm_calc()
4032 ctx->req_pck_nom = vm->pixelclock; in dsi_vm_calc()
4033 ctx->req_pck_max = vm->pixelclock + 1000; in dsi_vm_calc()
4035 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); in dsi_vm_calc()
4036 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); in dsi_vm_calc()
4038 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { in dsi_vm_calc()
4039 pll_max = cfg->hs_clk_max * 4; in dsi_vm_calc()
4042 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, in dsi_vm_calc()
4048 return dss_pll_calc_a(ctx->pll, clkin, in dsi_vm_calc()
4057 return dsi->mode == OMAP_DSS_DSI_VIDEO_MODE; in dsi_is_video_mode()
4064 struct omap_dss_dsi_config cfg = dsi->config; in __dsi_calc_config()
4072 cfg.mode = dsi->mode; in __dsi_calc_config()
4073 cfg.pixel_format = dsi->pix_fmt; in __dsi_calc_config()
4075 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) in __dsi_calc_config()
4081 return -EINVAL; in __dsi_calc_config()
4083 dsi_pll_calc_dsi_fck(dsi, &ctx->dsi_cinfo); in __dsi_calc_config()
4085 r = dsi_lp_clock_calc(ctx->dsi_cinfo.clkout[HSDIV_DSI], in __dsi_calc_config()
4086 cfg.lp_clk_min, cfg.lp_clk_max, &ctx->lp_cinfo); in __dsi_calc_config()
4100 mutex_lock(&dsi->lock); in dsi_set_config()
4108 dsi->user_lp_cinfo = ctx.lp_cinfo; in dsi_set_config()
4109 dsi->user_dsi_cinfo = ctx.dsi_cinfo; in dsi_set_config()
4110 dsi->user_dispc_cinfo = ctx.dispc_cinfo; in dsi_set_config()
4112 dsi->vm = ctx.vm; in dsi_set_config()
4118 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; in dsi_set_config()
4119 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; in dsi_set_config()
4120 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; in dsi_set_config()
4121 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; in dsi_set_config()
4122 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; in dsi_set_config()
4126 * converted to the omapdrm-managed encoder model. in dsi_set_config()
4128 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; in dsi_set_config()
4129 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; in dsi_set_config()
4130 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; in dsi_set_config()
4131 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; in dsi_set_config()
4132 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; in dsi_set_config()
4133 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; in dsi_set_config()
4135 dss_mgr_set_timings(&dsi->output, &dsi->vm); in dsi_set_config()
4137 dsi->vm_timings = ctx.dsi_vm; in dsi_set_config()
4139 mutex_unlock(&dsi->lock); in dsi_set_config()
4143 mutex_unlock(&dsi->lock); in dsi_set_config()
4156 switch (dsi->data->model) { in dsi_get_dispc_channel()
4161 switch (dsi->module_id) { in dsi_get_dispc_channel()
4172 switch (dsi->module_id) { in dsi_get_dispc_channel()
4191 struct omap_dss_device *dssdev = &dsi->output; in _omap_dsi_host_transfer()
4194 dsi_vc_enable_hs(dssdev, vc, !(msg->flags & MIPI_DSI_MSG_USE_LPM)); in _omap_dsi_host_transfer()
4196 switch (msg->type) { in _omap_dsi_host_transfer()
4217 r = -EINVAL; in _omap_dsi_host_transfer()
4224 if (msg->type == MIPI_DSI_DCS_SHORT_WRITE || in _omap_dsi_host_transfer()
4225 msg->type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) { in _omap_dsi_host_transfer()
4226 u8 cmd = ((u8 *)msg->tx_buf)[0]; in _omap_dsi_host_transfer()
4246 if (!dsi->iface_enabled) { in omap_dsi_host_transfer()
4248 schedule_delayed_work(&dsi->dsi_disable_work, msecs_to_jiffies(2000)); in omap_dsi_host_transfer()
4262 clk = devm_clk_get(dsi->dev, "fck"); in dsi_get_clocks()
4268 dsi->dss_clk = clk; in dsi_get_clocks()
4283 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0); in omap_dsi_te_irq_handler()
4285 cancel_delayed_work(&dsi->te_timeout_work); in omap_dsi_te_irq_handler()
4298 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0); in omap_dsi_te_timeout_work_callback()
4300 dev_err(dsi->dev, "TE not received for 250ms!\n"); in omap_dsi_te_timeout_work_callback()
4311 dsi->te_gpio = gpiod_get(&client->dev, "te-gpios", GPIOD_IN); in omap_dsi_register_te_irq()
4312 if (IS_ERR(dsi->te_gpio)) { in omap_dsi_register_te_irq()
4313 err = PTR_ERR(dsi->te_gpio); in omap_dsi_register_te_irq()
4315 if (err == -ENOENT) { in omap_dsi_register_te_irq()
4316 dsi->te_gpio = NULL; in omap_dsi_register_te_irq()
4320 dev_err(dsi->dev, "Could not get TE gpio: %d\n", err); in omap_dsi_register_te_irq()
4324 te_irq = gpiod_to_irq(dsi->te_gpio); in omap_dsi_register_te_irq()
4326 gpiod_put(dsi->te_gpio); in omap_dsi_register_te_irq()
4327 dsi->te_gpio = NULL; in omap_dsi_register_te_irq()
4328 return -EINVAL; in omap_dsi_register_te_irq()
4331 dsi->te_irq = te_irq; in omap_dsi_register_te_irq()
4337 "TE", dsi); in omap_dsi_register_te_irq()
4339 dev_err(dsi->dev, "request irq failed with %d\n", err); in omap_dsi_register_te_irq()
4340 gpiod_put(dsi->te_gpio); in omap_dsi_register_te_irq()
4341 dsi->te_gpio = NULL; in omap_dsi_register_te_irq()
4345 INIT_DEFERRABLE_WORK(&dsi->te_timeout_work, in omap_dsi_register_te_irq()
4348 dev_dbg(dsi->dev, "Using GPIO TE\n"); in omap_dsi_register_te_irq()
4355 if (dsi->te_gpio) { in omap_dsi_unregister_te_irq()
4356 free_irq(dsi->te_irq, dsi); in omap_dsi_unregister_te_irq()
4357 cancel_delayed_work(&dsi->te_timeout_work); in omap_dsi_unregister_te_irq()
4358 gpiod_put(dsi->te_gpio); in omap_dsi_unregister_te_irq()
4359 dsi->te_gpio = NULL; in omap_dsi_unregister_te_irq()
4369 if (dsi->dsidev) { in omap_dsi_host_attach()
4371 return -EBUSY; in omap_dsi_host_attach()
4374 if (mipi_dsi_pixel_format_to_bpp(client->format) < 0) { in omap_dsi_host_attach()
4376 return -EINVAL; in omap_dsi_host_attach()
4379 atomic_set(&dsi->do_ext_te_update, 0); in omap_dsi_host_attach()
4381 if (client->mode_flags & MIPI_DSI_MODE_VIDEO) { in omap_dsi_host_attach()
4382 dsi->mode = OMAP_DSS_DSI_VIDEO_MODE; in omap_dsi_host_attach()
4388 dsi->mode = OMAP_DSS_DSI_CMD_MODE; in omap_dsi_host_attach()
4391 dsi->dsidev = client; in omap_dsi_host_attach()
4392 dsi->pix_fmt = client->format; in omap_dsi_host_attach()
4394 dsi->config.hs_clk_min = 150000000; // TODO: get from client? in omap_dsi_host_attach()
4395 dsi->config.hs_clk_max = client->hs_rate; in omap_dsi_host_attach()
4396 dsi->config.lp_clk_min = 7000000; // TODO: get from client? in omap_dsi_host_attach()
4397 dsi->config.lp_clk_max = client->lp_rate; in omap_dsi_host_attach()
4399 if (client->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) in omap_dsi_host_attach()
4400 dsi->config.trans_mode = OMAP_DSS_DSI_BURST_MODE; in omap_dsi_host_attach()
4401 else if (client->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in omap_dsi_host_attach()
4402 dsi->config.trans_mode = OMAP_DSS_DSI_PULSE_MODE; in omap_dsi_host_attach()
4404 dsi->config.trans_mode = OMAP_DSS_DSI_EVENT_MODE; in omap_dsi_host_attach()
4414 if (WARN_ON(dsi->dsidev != client)) in omap_dsi_host_detach()
4415 return -EINVAL; in omap_dsi_host_detach()
4417 cancel_delayed_work_sync(&dsi->dsi_disable_work); in omap_dsi_host_detach()
4421 if (dsi->iface_enabled) in omap_dsi_host_detach()
4427 dsi->dsidev = NULL; in omap_dsi_host_detach()
4437 /* -----------------------------------------------------------------------------
4450 .n_max = (1 << 7) - 1,
4451 .m_max = (1 << 11) - 1,
4452 .mX_max = (1 << 4) - 1,
4477 .n_max = (1 << 8) - 1,
4478 .m_max = (1 << 12) - 1,
4479 .mX_max = (1 << 5) - 1,
4504 .n_max = (1 << 8) - 1,
4505 .m_max = (1 << 12) - 1,
4506 .mX_max = (1 << 5) - 1,
4530 struct dss_pll *pll = &dsi->pll; in dsi_init_pll_data()
4534 clk = devm_clk_get(dsi->dev, "sys_clk"); in dsi_init_pll_data()
4540 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; in dsi_init_pll_data()
4541 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; in dsi_init_pll_data()
4542 pll->clkin = clk; in dsi_init_pll_data()
4543 pll->base = dsi->pll_base; in dsi_init_pll_data()
4544 pll->hw = dsi->data->pll_hw; in dsi_init_pll_data()
4545 pll->ops = &dsi_pll_ops; in dsi_init_pll_data()
4554 /* -----------------------------------------------------------------------------
4566 dsi->dss = dss; in dsi_bind()
4578 dsi->line_buffer_size = dsi_get_line_buf_size(dsi); in dsi_bind()
4582 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1); in dsi_bind()
4583 dsi->debugfs.regs = dss_debugfs_create_file(dss, name, in dsi_bind()
4586 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1); in dsi_bind()
4587 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name, in dsi_bind()
4590 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1); in dsi_bind()
4591 dsi->debugfs.clks = dss_debugfs_create_file(dss, name, in dsi_bind()
4601 dss_debugfs_remove_file(dsi->debugfs.clks); in dsi_unbind()
4602 dss_debugfs_remove_file(dsi->debugfs.irqs); in dsi_unbind()
4603 dss_debugfs_remove_file(dsi->debugfs.regs); in dsi_unbind()
4605 WARN_ON(dsi->scp_clk_refcount > 0); in dsi_unbind()
4607 dss_pll_unregister(&dsi->pll); in dsi_unbind()
4615 /* -----------------------------------------------------------------------------
4625 return -EINVAL; in dsi_bridge_attach()
4627 return drm_bridge_attach(bridge->encoder, dsi->output.next_bridge, in dsi_bridge_attach()
4640 mutex_lock(&dsi->lock); in dsi_bridge_mode_valid()
4642 mutex_unlock(&dsi->lock); in dsi_bridge_mode_valid()
4653 dsi_set_config(&dsi->output, adjusted_mode); in dsi_bridge_mode_set()
4659 struct omap_dss_device *dssdev = &dsi->output; in dsi_bridge_enable()
4661 cancel_delayed_work_sync(&dsi->dsi_disable_work); in dsi_bridge_enable()
4665 if (!dsi->iface_enabled) in dsi_bridge_enable()
4670 dsi->video_enabled = true; in dsi_bridge_enable()
4678 struct omap_dss_device *dssdev = &dsi->output; in dsi_bridge_disable()
4680 cancel_delayed_work_sync(&dsi->dsi_disable_work); in dsi_bridge_disable()
4684 dsi->video_enabled = false; in dsi_bridge_disable()
4703 dsi->bridge.funcs = &dsi_bridge_funcs; in dsi_bridge_init()
4704 dsi->bridge.of_node = dsi->host.dev->of_node; in dsi_bridge_init()
4705 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; in dsi_bridge_init()
4707 drm_bridge_add(&dsi->bridge); in dsi_bridge_init()
4712 drm_bridge_remove(&dsi->bridge); in dsi_bridge_cleanup()
4715 /* -----------------------------------------------------------------------------
4721 struct omap_dss_device *out = &dsi->output; in dsi_init_output()
4726 out->dev = dsi->dev; in dsi_init_output()
4727 out->id = dsi->module_id == 0 ? in dsi_init_output()
4730 out->type = OMAP_DISPLAY_TYPE_DSI; in dsi_init_output()
4731 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; in dsi_init_output()
4732 out->dispc_channel = dsi_get_dispc_channel(dsi); in dsi_init_output()
4733 out->dsi_ops = &dsi_ops; in dsi_init_output()
4734 out->of_port = 0; in dsi_init_output()
4735 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE in dsi_init_output()
4739 r = omapdss_device_init_output(out, &dsi->bridge); in dsi_init_output()
4752 struct omap_dss_device *out = &dsi->output; in dsi_uninit_output()
4761 struct device_node *node = dsi->dev->of_node; in dsi_probe_of()
4774 dev_err(dsi->dev, "failed to find lane data\n"); in dsi_probe_of()
4775 r = -EINVAL; in dsi_probe_of()
4782 num_pins > dsi->num_lanes_supported * 2) { in dsi_probe_of()
4783 dev_err(dsi->dev, "bad number of lanes\n"); in dsi_probe_of()
4784 r = -EINVAL; in dsi_probe_of()
4790 dev_err(dsi->dev, "failed to read lane data\n"); in dsi_probe_of()
4796 dev_err(dsi->dev, "failed to configure pins"); in dsi_probe_of()
4817 .max_pll_lpdiv = (1 << 13) - 1,
4829 .max_pll_lpdiv = (1 << 13) - 1,
4842 .max_pll_lpdiv = (1 << 13) - 1,
4856 .max_pll_lpdiv = (1 << 13) - 1,
4862 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
4863 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
4864 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
4880 if (dsi->iface_enabled && !dsi->video_enabled) in omap_dsi_disable_work_callback()
4890 struct device *dev = &pdev->dev; in dsi_probe()
4898 return -ENOMEM; in dsi_probe()
4900 dsi->dev = dev; in dsi_probe()
4903 spin_lock_init(&dsi->irq_lock); in dsi_probe()
4904 spin_lock_init(&dsi->errors_lock); in dsi_probe()
4905 dsi->errors = 0; in dsi_probe()
4908 spin_lock_init(&dsi->irq_stats_lock); in dsi_probe()
4909 dsi->irq_stats.last_reset = jiffies; in dsi_probe()
4912 mutex_init(&dsi->lock); in dsi_probe()
4913 sema_init(&dsi->bus_lock, 1); in dsi_probe()
4915 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, in dsi_probe()
4918 INIT_DEFERRABLE_WORK(&dsi->dsi_disable_work, omap_dsi_disable_work_callback); in dsi_probe()
4921 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); in dsi_probe()
4925 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem); in dsi_probe()
4926 if (IS_ERR(dsi->proto_base)) in dsi_probe()
4927 return PTR_ERR(dsi->proto_base); in dsi_probe()
4929 dsi->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy"); in dsi_probe()
4930 if (IS_ERR(dsi->phy_base)) in dsi_probe()
4931 return PTR_ERR(dsi->phy_base); in dsi_probe()
4933 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll"); in dsi_probe()
4934 if (IS_ERR(dsi->pll_base)) in dsi_probe()
4935 return PTR_ERR(dsi->pll_base); in dsi_probe()
4937 dsi->irq = platform_get_irq(pdev, 0); in dsi_probe()
4938 if (dsi->irq < 0) { in dsi_probe()
4940 return -ENODEV; in dsi_probe()
4943 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler, in dsi_probe()
4950 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd"); in dsi_probe()
4951 if (IS_ERR(dsi->vdds_dsi_reg)) { in dsi_probe()
4952 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER) in dsi_probe()
4954 return PTR_ERR(dsi->vdds_dsi_reg); in dsi_probe()
4959 dsi->data = soc->data; in dsi_probe()
4961 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; in dsi_probe()
4963 d = dsi->data->modules; in dsi_probe()
4964 while (d->address != 0 && d->address != dsi_mem->start) in dsi_probe()
4967 if (d->address == 0) { in dsi_probe()
4969 return -ENODEV; in dsi_probe()
4972 dsi->module_id = d->id; in dsi_probe()
4974 if (dsi->data->model == DSI_MODEL_OMAP4 || in dsi_probe()
4975 dsi->data->model == DSI_MODEL_OMAP5) { in dsi_probe()
4983 dsi->data->model == DSI_MODEL_OMAP4 ? in dsi_probe()
4986 return -ENODEV; in dsi_probe()
4988 dsi->syscon = syscon_node_to_regmap(np); in dsi_probe()
4993 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) in dsi_probe()
4994 dsi->vc[i].source = DSI_VC_SOURCE_L4; in dsi_probe()
5004 if (dsi->data->quirks & DSI_QUIRK_GNQ) { in dsi_probe()
5007 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); in dsi_probe()
5010 dsi->num_lanes_supported = 3; in dsi_probe()
5013 dsi->host.ops = &omap_dsi_host_ops; in dsi_probe()
5014 dsi->host.dev = &pdev->dev; in dsi_probe()
5022 r = mipi_dsi_host_register(&dsi->host); in dsi_probe()
5024 dev_err(&pdev->dev, "failed to register DSI host: %d\n", r); in dsi_probe()
5032 r = component_add(&pdev->dev, &dsi_component_ops); in dsi_probe()
5041 mipi_dsi_host_unregister(&dsi->host); in dsi_probe()
5051 component_del(&pdev->dev, &dsi_component_ops); in dsi_remove()
5055 mipi_dsi_host_unregister(&dsi->host); in dsi_remove()
5057 pm_runtime_disable(&pdev->dev); in dsi_remove()
5059 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { in dsi_remove()
5060 regulator_disable(dsi->vdds_dsi_reg); in dsi_remove()
5061 dsi->vdds_dsi_enabled = false; in dsi_remove()
5069 dsi->is_enabled = false; in dsi_runtime_suspend()
5073 synchronize_irq(dsi->irq); in dsi_runtime_suspend()
5082 dsi->is_enabled = true; in dsi_runtime_resume()