Lines Matching refs:dispc
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
102 int (*calc_scaling)(struct dispc_device *dispc,
344 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
345 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
346 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
348 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
351 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
353 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) in dispc_write_reg() argument
358 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
361 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) in dispc_read_reg() argument
363 return __raw_readl(dispc->base + idx); in dispc_read_reg()
366 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_read() argument
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
374 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_write() argument
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
382 int dispc_get_num_ovls(struct dispc_device *dispc) in dispc_get_num_ovls() argument
384 return dispc->feat->num_ovls; in dispc_get_num_ovls()
387 int dispc_get_num_mgrs(struct dispc_device *dispc) in dispc_get_num_mgrs() argument
389 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
392 static void dispc_get_reg_field(struct dispc_device *dispc, in dispc_get_reg_field() argument
396 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
398 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
399 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
402 static bool dispc_has_feature(struct dispc_device *dispc, in dispc_has_feature() argument
407 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
408 if (dispc->feat->features[i] == id) in dispc_has_feature()
415 #define SR(dispc, reg) \ argument
416 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
417 #define RR(dispc, reg) \ argument
418 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
420 static void dispc_save_context(struct dispc_device *dispc) in dispc_save_context() argument
426 SR(dispc, IRQENABLE); in dispc_save_context()
427 SR(dispc, CONTROL); in dispc_save_context()
428 SR(dispc, CONFIG); in dispc_save_context()
429 SR(dispc, LINE_NUMBER); in dispc_save_context()
430 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_save_context()
431 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_save_context()
432 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
433 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_save_context()
434 SR(dispc, CONTROL2); in dispc_save_context()
435 SR(dispc, CONFIG2); in dispc_save_context()
437 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_save_context()
438 SR(dispc, CONTROL3); in dispc_save_context()
439 SR(dispc, CONFIG3); in dispc_save_context()
442 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_save_context()
443 SR(dispc, DEFAULT_COLOR(i)); in dispc_save_context()
444 SR(dispc, TRANS_COLOR(i)); in dispc_save_context()
445 SR(dispc, SIZE_MGR(i)); in dispc_save_context()
448 SR(dispc, TIMING_H(i)); in dispc_save_context()
449 SR(dispc, TIMING_V(i)); in dispc_save_context()
450 SR(dispc, POL_FREQ(i)); in dispc_save_context()
451 SR(dispc, DIVISORo(i)); in dispc_save_context()
453 SR(dispc, DATA_CYCLE1(i)); in dispc_save_context()
454 SR(dispc, DATA_CYCLE2(i)); in dispc_save_context()
455 SR(dispc, DATA_CYCLE3(i)); in dispc_save_context()
457 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_save_context()
458 SR(dispc, CPR_COEF_R(i)); in dispc_save_context()
459 SR(dispc, CPR_COEF_G(i)); in dispc_save_context()
460 SR(dispc, CPR_COEF_B(i)); in dispc_save_context()
464 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_save_context()
465 SR(dispc, OVL_BA0(i)); in dispc_save_context()
466 SR(dispc, OVL_BA1(i)); in dispc_save_context()
467 SR(dispc, OVL_POSITION(i)); in dispc_save_context()
468 SR(dispc, OVL_SIZE(i)); in dispc_save_context()
469 SR(dispc, OVL_ATTRIBUTES(i)); in dispc_save_context()
470 SR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_save_context()
471 SR(dispc, OVL_ROW_INC(i)); in dispc_save_context()
472 SR(dispc, OVL_PIXEL_INC(i)); in dispc_save_context()
473 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_save_context()
474 SR(dispc, OVL_PRELOAD(i)); in dispc_save_context()
476 SR(dispc, OVL_WINDOW_SKIP(i)); in dispc_save_context()
477 SR(dispc, OVL_TABLE_BA(i)); in dispc_save_context()
480 SR(dispc, OVL_FIR(i)); in dispc_save_context()
481 SR(dispc, OVL_PICTURE_SIZE(i)); in dispc_save_context()
482 SR(dispc, OVL_ACCU0(i)); in dispc_save_context()
483 SR(dispc, OVL_ACCU1(i)); in dispc_save_context()
486 SR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_save_context()
489 SR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_save_context()
492 SR(dispc, OVL_CONV_COEF(i, j)); in dispc_save_context()
494 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_save_context()
496 SR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_save_context()
499 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_save_context()
500 SR(dispc, OVL_BA0_UV(i)); in dispc_save_context()
501 SR(dispc, OVL_BA1_UV(i)); in dispc_save_context()
502 SR(dispc, OVL_FIR2(i)); in dispc_save_context()
503 SR(dispc, OVL_ACCU2_0(i)); in dispc_save_context()
504 SR(dispc, OVL_ACCU2_1(i)); in dispc_save_context()
507 SR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_save_context()
510 SR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_save_context()
513 SR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_save_context()
515 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_save_context()
516 SR(dispc, OVL_ATTRIBUTES2(i)); in dispc_save_context()
519 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_save_context()
520 SR(dispc, DIVISOR); in dispc_save_context()
522 dispc->ctx_valid = true; in dispc_save_context()
527 static void dispc_restore_context(struct dispc_device *dispc) in dispc_restore_context() argument
533 if (!dispc->ctx_valid) in dispc_restore_context()
538 RR(dispc, CONFIG); in dispc_restore_context()
539 RR(dispc, LINE_NUMBER); in dispc_restore_context()
540 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_restore_context()
541 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_restore_context()
542 RR(dispc, GLOBAL_ALPHA); in dispc_restore_context()
543 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
544 RR(dispc, CONFIG2); in dispc_restore_context()
545 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
546 RR(dispc, CONFIG3); in dispc_restore_context()
548 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_restore_context()
549 RR(dispc, DEFAULT_COLOR(i)); in dispc_restore_context()
550 RR(dispc, TRANS_COLOR(i)); in dispc_restore_context()
551 RR(dispc, SIZE_MGR(i)); in dispc_restore_context()
554 RR(dispc, TIMING_H(i)); in dispc_restore_context()
555 RR(dispc, TIMING_V(i)); in dispc_restore_context()
556 RR(dispc, POL_FREQ(i)); in dispc_restore_context()
557 RR(dispc, DIVISORo(i)); in dispc_restore_context()
559 RR(dispc, DATA_CYCLE1(i)); in dispc_restore_context()
560 RR(dispc, DATA_CYCLE2(i)); in dispc_restore_context()
561 RR(dispc, DATA_CYCLE3(i)); in dispc_restore_context()
563 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_restore_context()
564 RR(dispc, CPR_COEF_R(i)); in dispc_restore_context()
565 RR(dispc, CPR_COEF_G(i)); in dispc_restore_context()
566 RR(dispc, CPR_COEF_B(i)); in dispc_restore_context()
570 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_restore_context()
571 RR(dispc, OVL_BA0(i)); in dispc_restore_context()
572 RR(dispc, OVL_BA1(i)); in dispc_restore_context()
573 RR(dispc, OVL_POSITION(i)); in dispc_restore_context()
574 RR(dispc, OVL_SIZE(i)); in dispc_restore_context()
575 RR(dispc, OVL_ATTRIBUTES(i)); in dispc_restore_context()
576 RR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_restore_context()
577 RR(dispc, OVL_ROW_INC(i)); in dispc_restore_context()
578 RR(dispc, OVL_PIXEL_INC(i)); in dispc_restore_context()
579 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_restore_context()
580 RR(dispc, OVL_PRELOAD(i)); in dispc_restore_context()
582 RR(dispc, OVL_WINDOW_SKIP(i)); in dispc_restore_context()
583 RR(dispc, OVL_TABLE_BA(i)); in dispc_restore_context()
586 RR(dispc, OVL_FIR(i)); in dispc_restore_context()
587 RR(dispc, OVL_PICTURE_SIZE(i)); in dispc_restore_context()
588 RR(dispc, OVL_ACCU0(i)); in dispc_restore_context()
589 RR(dispc, OVL_ACCU1(i)); in dispc_restore_context()
592 RR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_restore_context()
595 RR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_restore_context()
598 RR(dispc, OVL_CONV_COEF(i, j)); in dispc_restore_context()
600 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_restore_context()
602 RR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_restore_context()
605 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_restore_context()
606 RR(dispc, OVL_BA0_UV(i)); in dispc_restore_context()
607 RR(dispc, OVL_BA1_UV(i)); in dispc_restore_context()
608 RR(dispc, OVL_FIR2(i)); in dispc_restore_context()
609 RR(dispc, OVL_ACCU2_0(i)); in dispc_restore_context()
610 RR(dispc, OVL_ACCU2_1(i)); in dispc_restore_context()
613 RR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_restore_context()
616 RR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_restore_context()
619 RR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_restore_context()
621 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_restore_context()
622 RR(dispc, OVL_ATTRIBUTES2(i)); in dispc_restore_context()
625 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_restore_context()
626 RR(dispc, DIVISOR); in dispc_restore_context()
629 RR(dispc, CONTROL); in dispc_restore_context()
630 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
631 RR(dispc, CONTROL2); in dispc_restore_context()
632 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
633 RR(dispc, CONTROL3); in dispc_restore_context()
635 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); in dispc_restore_context()
641 RR(dispc, IRQENABLE); in dispc_restore_context()
649 int dispc_runtime_get(struct dispc_device *dispc) in dispc_runtime_get() argument
655 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
657 pm_runtime_put_noidle(&dispc->pdev->dev); in dispc_runtime_get()
663 void dispc_runtime_put(struct dispc_device *dispc) in dispc_runtime_put() argument
669 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
673 u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, in dispc_mgr_get_vsync_irq() argument
679 u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, in dispc_mgr_get_framedone_irq() argument
682 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
688 u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, in dispc_mgr_get_sync_lost_irq() argument
694 u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) in dispc_wb_get_framedone_irq() argument
699 void dispc_mgr_enable(struct dispc_device *dispc, in dispc_mgr_enable() argument
702 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); in dispc_mgr_enable()
704 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_enable()
707 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, in dispc_mgr_is_enabled() argument
710 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_is_enabled()
713 bool dispc_mgr_go_busy(struct dispc_device *dispc, in dispc_mgr_go_busy() argument
716 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; in dispc_mgr_go_busy()
719 void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) in dispc_mgr_go() argument
721 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); in dispc_mgr_go()
722 WARN_ON(dispc_mgr_go_busy(dispc, channel)); in dispc_mgr_go()
726 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); in dispc_mgr_go()
729 bool dispc_wb_go_busy(struct dispc_device *dispc) in dispc_wb_go_busy() argument
731 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
734 void dispc_wb_go(struct dispc_device *dispc) in dispc_wb_go() argument
739 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
744 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
750 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
753 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, in dispc_ovl_write_firh_reg() argument
757 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); in dispc_ovl_write_firh_reg()
760 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv_reg() argument
764 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); in dispc_ovl_write_firhv_reg()
767 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, in dispc_ovl_write_firv_reg() argument
771 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); in dispc_ovl_write_firv_reg()
774 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, in dispc_ovl_write_firh2_reg() argument
780 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); in dispc_ovl_write_firh2_reg()
783 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv2_reg() argument
789 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); in dispc_ovl_write_firhv2_reg()
792 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firv2_reg() argument
798 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); in dispc_ovl_write_firv2_reg()
801 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, in dispc_ovl_set_scale_coef() argument
813 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
831 dispc_ovl_write_firh_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
832 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
834 dispc_ovl_write_firh2_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
835 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
846 dispc_ovl_write_firv_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
848 dispc_ovl_write_firv2_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
858 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, in dispc_ovl_write_color_conv_coef() argument
864 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
865 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
870 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
907 static void dispc_ovl_set_csc(struct dispc_device *dispc, in dispc_ovl_set_csc() argument
930 dispc_ovl_write_color_conv_coef(dispc, plane, csc); in dispc_ovl_set_csc()
933 static void dispc_ovl_set_ba0(struct dispc_device *dispc, in dispc_ovl_set_ba0() argument
936 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); in dispc_ovl_set_ba0()
939 static void dispc_ovl_set_ba1(struct dispc_device *dispc, in dispc_ovl_set_ba1() argument
942 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); in dispc_ovl_set_ba1()
945 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, in dispc_ovl_set_ba0_uv() argument
948 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); in dispc_ovl_set_ba0_uv()
951 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, in dispc_ovl_set_ba1_uv() argument
954 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); in dispc_ovl_set_ba1_uv()
957 static void dispc_ovl_set_pos(struct dispc_device *dispc, in dispc_ovl_set_pos() argument
968 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); in dispc_ovl_set_pos()
971 static void dispc_ovl_set_input_size(struct dispc_device *dispc, in dispc_ovl_set_input_size() argument
978 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_input_size()
980 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_input_size()
983 static void dispc_ovl_set_output_size(struct dispc_device *dispc, in dispc_ovl_set_output_size() argument
994 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_output_size()
996 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_output_size()
999 static void dispc_ovl_set_zorder(struct dispc_device *dispc, in dispc_ovl_set_zorder() argument
1006 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
1009 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) in dispc_ovl_enable_zorder_planes() argument
1013 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_ovl_enable_zorder_planes()
1016 for (i = 0; i < dispc_get_num_ovls(dispc); i++) in dispc_ovl_enable_zorder_planes()
1017 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1020 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, in dispc_ovl_set_pre_mult_alpha() argument
1028 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1031 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, in dispc_ovl_setup_global_alpha() argument
1043 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
1046 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, in dispc_ovl_set_pix_inc() argument
1049 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); in dispc_ovl_set_pix_inc()
1052 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, in dispc_ovl_set_row_inc() argument
1055 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); in dispc_ovl_set_row_inc()
1058 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, in dispc_ovl_set_color_mode() argument
1128 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
1131 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, in dispc_ovl_configure_burst_type() argument
1135 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) in dispc_ovl_configure_burst_type()
1139 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
1141 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); in dispc_ovl_configure_burst_type()
1144 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, in dispc_ovl_set_channel_out() argument
1166 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_channel_out()
1167 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_ovl_set_channel_out()
1182 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_ovl_set_channel_out()
1204 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_channel_out()
1207 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, in dispc_ovl_get_channel_out() argument
1227 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_get_channel_out()
1232 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_ovl_get_channel_out()
1248 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, in dispc_ovl_set_burst_size() argument
1256 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, in dispc_ovl_set_burst_size()
1260 static void dispc_configure_burst_sizes(struct dispc_device *dispc) in dispc_configure_burst_sizes() argument
1266 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_configure_burst_sizes()
1267 dispc_ovl_set_burst_size(dispc, i, burst_size); in dispc_configure_burst_sizes()
1268 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1269 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); in dispc_configure_burst_sizes()
1272 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, in dispc_ovl_get_burst_size() argument
1276 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1279 bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, in dispc_ovl_color_mode_supported() argument
1285 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1295 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, in dispc_ovl_get_color_modes() argument
1298 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1301 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, in dispc_mgr_enable_cpr() argument
1307 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); in dispc_mgr_enable_cpr()
1310 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, in dispc_mgr_set_cpr_coef() argument
1326 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); in dispc_mgr_set_cpr_coef()
1327 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); in dispc_mgr_set_cpr_coef()
1328 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); in dispc_mgr_set_cpr_coef()
1331 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, in dispc_ovl_set_vid_color_conv() argument
1338 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_vid_color_conv()
1340 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_vid_color_conv()
1343 static void dispc_ovl_enable_replication(struct dispc_device *dispc, in dispc_ovl_enable_replication() argument
1355 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); in dispc_ovl_enable_replication()
1358 static void dispc_mgr_set_size(struct dispc_device *dispc, in dispc_mgr_set_size() argument
1363 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1364 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1366 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); in dispc_mgr_set_size()
1369 static void dispc_init_fifos(struct dispc_device *dispc) in dispc_init_fifos() argument
1377 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1379 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); in dispc_init_fifos()
1381 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1382 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1385 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1391 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1401 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1404 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); in dispc_init_fifos()
1411 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); in dispc_init_fifos()
1413 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1414 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1420 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_fifos()
1425 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, in dispc_init_fifos()
1428 dispc_ovl_set_fifo_threshold(dispc, i, low, high); in dispc_init_fifos()
1431 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1436 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, in dispc_init_fifos()
1440 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_fifos()
1444 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, in dispc_ovl_get_fifo_size() argument
1450 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1451 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1452 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1458 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, in dispc_ovl_set_fifo_threshold() argument
1465 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1473 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1475 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1480 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1482 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1486 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1495 if (dispc_has_feature(dispc, FEAT_PRELOAD) && in dispc_ovl_set_fifo_threshold()
1496 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1497 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), in dispc_ovl_set_fifo_threshold()
1501 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) in dispc_enable_fifomerge() argument
1503 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { in dispc_enable_fifomerge()
1509 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
1512 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, in dispc_ovl_compute_fifo_thresholds() argument
1521 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1525 burst_size = dispc_ovl_get_burst_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1526 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1530 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_ovl_compute_fifo_thresholds()
1531 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); in dispc_ovl_compute_fifo_thresholds()
1542 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { in dispc_ovl_compute_fifo_thresholds()
1559 static void dispc_ovl_set_mflag(struct dispc_device *dispc, in dispc_ovl_set_mflag() argument
1569 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); in dispc_ovl_set_mflag()
1572 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, in dispc_ovl_set_mflag_threshold() argument
1576 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), in dispc_ovl_set_mflag_threshold()
1580 static void dispc_init_mflag(struct dispc_device *dispc) in dispc_init_mflag() argument
1594 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, in dispc_init_mflag()
1598 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_mflag()
1599 u32 size = dispc_ovl_get_fifo_size(dispc, i); in dispc_init_mflag()
1600 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1603 dispc_ovl_set_mflag(dispc, i, true); in dispc_init_mflag()
1614 dispc_ovl_set_mflag_threshold(dispc, i, low, high); in dispc_init_mflag()
1617 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1618 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); in dispc_init_mflag()
1619 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1622 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); in dispc_init_mflag()
1633 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_mflag()
1637 static void dispc_ovl_set_fir(struct dispc_device *dispc, in dispc_ovl_set_fir() argument
1647 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, in dispc_ovl_set_fir()
1649 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, in dispc_ovl_set_fir()
1654 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); in dispc_ovl_set_fir()
1657 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); in dispc_ovl_set_fir()
1661 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu0() argument
1668 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu0()
1670 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu0()
1676 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); in dispc_ovl_set_vid_accu0()
1679 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu1() argument
1686 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu1()
1688 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu1()
1694 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); in dispc_ovl_set_vid_accu1()
1697 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_0() argument
1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); in dispc_ovl_set_vid_accu2_0()
1707 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_1() argument
1714 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); in dispc_ovl_set_vid_accu2_1()
1717 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, in dispc_ovl_set_scale_param() argument
1729 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, in dispc_ovl_set_scale_param()
1731 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); in dispc_ovl_set_scale_param()
1734 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, in dispc_ovl_set_accu_uv() argument
1819 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); in dispc_ovl_set_accu_uv()
1820 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); in dispc_ovl_set_accu_uv()
1823 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, in dispc_ovl_set_scaling_common() argument
1835 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_common()
1838 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_scaling_common()
1847 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { in dispc_ovl_set_scaling_common()
1854 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { in dispc_ovl_set_scaling_common()
1859 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_ovl_set_scaling_common()
1874 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); in dispc_ovl_set_scaling_common()
1875 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); in dispc_ovl_set_scaling_common()
1878 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, in dispc_ovl_set_scaling_uv() argument
1893 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) in dispc_ovl_set_scaling_uv()
1899 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1904 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, in dispc_ovl_set_scaling_uv()
1947 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_uv()
1952 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1956 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); in dispc_ovl_set_scaling_uv()
1958 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); in dispc_ovl_set_scaling_uv()
1961 static void dispc_ovl_set_scaling(struct dispc_device *dispc, in dispc_ovl_set_scaling() argument
1971 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1975 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1980 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, in dispc_ovl_set_rotation_attrs() argument
2037 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); in dispc_ovl_set_rotation_attrs()
2038 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) in dispc_ovl_set_rotation_attrs()
2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2042 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { in dispc_ovl_set_rotation_attrs()
2049 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2286 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_24xx() argument
2300 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2307 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2310 *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_24xx()
2335 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_34xx() argument
2348 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2365 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2379 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_34xx()
2423 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_44xx() argument
2437 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2438 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2443 in_width_max = dispc_core_clk_rate(dispc) in dispc_ovl_calc_scaling_44xx()
2482 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2487 enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane) in dispc_ovl_get_caps() argument
2489 return dispc->feat->overlay_caps[plane]; in dispc_ovl_get_caps()
2495 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, in dispc_ovl_calc_scaling() argument
2507 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2508 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2516 if (dispc->feat->supported_scaler_color_modes) { in dispc_ovl_calc_scaling()
2517 const u32 *modes = dispc->feat->supported_scaler_color_modes; in dispc_ovl_calc_scaling()
2556 dispc_has_feature(dispc, FEAT_BURST_2D)) ? in dispc_ovl_calc_scaling()
2569 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2589 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2591 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { in dispc_ovl_calc_scaling()
2595 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2604 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height) in dispc_ovl_get_max_size() argument
2606 *width = dispc->feat->ovl_width_max; in dispc_ovl_get_max_size()
2607 *height = dispc->feat->ovl_height_max; in dispc_ovl_get_max_size()
2610 static int dispc_ovl_setup_common(struct dispc_device *dispc, in dispc_ovl_setup_common() argument
2637 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); in dispc_ovl_setup_common()
2638 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); in dispc_ovl_setup_common()
2673 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) in dispc_ovl_setup_common()
2676 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, in dispc_ovl_setup_common()
2738 dispc_ovl_set_color_mode(dispc, plane, fourcc); in dispc_ovl_setup_common()
2740 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); in dispc_ovl_setup_common()
2742 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2745 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); in dispc_ovl_setup_common()
2746 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); in dispc_ovl_setup_common()
2749 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); in dispc_ovl_setup_common()
2750 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); in dispc_ovl_setup_common()
2753 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2756 dispc_ovl_set_row_inc(dispc, plane, row_inc); in dispc_ovl_setup_common()
2757 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); in dispc_ovl_setup_common()
2762 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); in dispc_ovl_setup_common()
2764 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); in dispc_ovl_setup_common()
2767 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, in dispc_ovl_setup_common()
2770 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); in dispc_ovl_setup_common()
2771 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); in dispc_ovl_setup_common()
2774 dispc_ovl_set_csc(dispc, plane, color_encoding, color_range); in dispc_ovl_setup_common()
2777 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, in dispc_ovl_setup_common()
2780 dispc_ovl_set_zorder(dispc, plane, caps, zorder); in dispc_ovl_setup_common()
2781 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); in dispc_ovl_setup_common()
2782 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); in dispc_ovl_setup_common()
2784 dispc_ovl_enable_replication(dispc, plane, caps, replication); in dispc_ovl_setup_common()
2789 int dispc_ovl_setup(struct dispc_device *dispc, in dispc_ovl_setup() argument
2796 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2805 dispc_ovl_set_channel_out(dispc, plane, channel); in dispc_ovl_setup()
2807 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2817 int dispc_wb_setup(struct dispc_device *dispc, in dispc_wb_setup() argument
2841 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2867 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_wb_setup()
2875 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_wb_setup()
2879 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); in dispc_wb_setup()
2895 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); in dispc_wb_setup()
2901 bool dispc_has_writeback(struct dispc_device *dispc) in dispc_has_writeback() argument
2903 return dispc->feat->has_writeback; in dispc_has_writeback()
2906 int dispc_ovl_enable(struct dispc_device *dispc, in dispc_ovl_enable() argument
2911 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); in dispc_ovl_enable()
2916 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, in dispc_lcd_enable_signal_polarity() argument
2919 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) in dispc_lcd_enable_signal_polarity()
2922 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2925 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) in dispc_lcd_enable_signal() argument
2927 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) in dispc_lcd_enable_signal()
2930 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2933 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) in dispc_pck_free_enable() argument
2935 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) in dispc_pck_free_enable()
2938 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
2941 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, in dispc_mgr_enable_fifohandcheck() argument
2945 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); in dispc_mgr_enable_fifohandcheck()
2949 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, in dispc_mgr_set_lcd_type_tft() argument
2952 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); in dispc_mgr_set_lcd_type_tft()
2955 static void dispc_set_loadmode(struct dispc_device *dispc, in dispc_set_loadmode() argument
2958 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2962 static void dispc_mgr_set_default_color(struct dispc_device *dispc, in dispc_mgr_set_default_color() argument
2965 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); in dispc_mgr_set_default_color()
2968 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, in dispc_mgr_set_trans_key() argument
2973 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); in dispc_mgr_set_trans_key()
2975 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); in dispc_mgr_set_trans_key()
2978 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, in dispc_mgr_enable_trans_key() argument
2981 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); in dispc_mgr_enable_trans_key()
2984 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, in dispc_mgr_enable_alpha_fixed_zorder() argument
2988 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) in dispc_mgr_enable_alpha_fixed_zorder()
2992 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
2994 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); in dispc_mgr_enable_alpha_fixed_zorder()
2997 void dispc_mgr_setup(struct dispc_device *dispc, in dispc_mgr_setup() argument
3001 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
3002 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
3004 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
3005 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, in dispc_mgr_setup()
3007 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_mgr_setup()
3008 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
3009 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
3013 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, in dispc_mgr_set_tft_data_lines() argument
3037 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); in dispc_mgr_set_tft_data_lines()
3040 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, in dispc_mgr_set_io_pad_mode() argument
3064 l = dispc_read_reg(dispc, DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
3067 dispc_write_reg(dispc, DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
3070 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, in dispc_mgr_enable_stallmode() argument
3073 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); in dispc_mgr_enable_stallmode()
3076 void dispc_mgr_set_lcd_config(struct dispc_device *dispc, in dispc_mgr_set_lcd_config() argument
3080 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3082 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3083 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3085 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3087 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3089 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3091 dispc_mgr_set_lcd_type_tft(dispc, channel); in dispc_mgr_set_lcd_config()
3094 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, in _dispc_mgr_size_ok() argument
3097 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3098 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3101 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, in _dispc_lcd_timings_ok() argument
3105 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3106 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3107 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3108 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3109 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3110 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3115 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, in _dispc_mgr_pclk_ok() argument
3120 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3122 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3125 int dispc_mgr_check_timings(struct dispc_device *dispc, in dispc_mgr_check_timings() argument
3129 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3132 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3140 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3150 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, in _dispc_mgr_set_lcd_timings() argument
3157 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3158 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3159 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3160 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3161 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3162 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3164 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); in _dispc_mgr_set_lcd_timings()
3165 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); in _dispc_mgr_set_lcd_timings()
3182 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3185 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); in _dispc_mgr_set_lcd_timings()
3187 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3202 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3218 void dispc_mgr_set_timings(struct dispc_device *dispc, in dispc_mgr_set_timings() argument
3228 if (dispc_mgr_check_timings(dispc, channel, &t)) { in dispc_mgr_set_timings()
3234 _dispc_mgr_set_lcd_timings(dispc, channel, &t); in dispc_mgr_set_timings()
3258 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3259 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
3264 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); in dispc_mgr_set_timings()
3267 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_set_lcd_divisor() argument
3274 dispc_write_reg(dispc, DISPC_DIVISORo(channel), in dispc_mgr_set_lcd_divisor()
3277 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && in dispc_mgr_set_lcd_divisor()
3279 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3282 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_get_lcd_divisor() argument
3287 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_get_lcd_divisor()
3292 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) in dispc_fclk_rate() argument
3297 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3300 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3305 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3314 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, in dispc_mgr_lclk_rate() argument
3323 return dispc_fclk_rate(dispc); in dispc_mgr_lclk_rate()
3325 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3328 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3333 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3339 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
3344 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, in dispc_mgr_pclk_rate() argument
3353 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_pclk_rate()
3357 r = dispc_mgr_lclk_rate(dispc, channel); in dispc_mgr_pclk_rate()
3361 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3365 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) in dispc_set_tv_pclk() argument
3367 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3370 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) in dispc_core_clk_rate() argument
3372 return dispc->core_clk_rate; in dispc_core_clk_rate()
3375 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, in dispc_plane_pclk_rate() argument
3383 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_pclk_rate()
3385 return dispc_mgr_pclk_rate(dispc, channel); in dispc_plane_pclk_rate()
3388 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, in dispc_plane_lclk_rate() argument
3396 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_lclk_rate()
3398 return dispc_mgr_lclk_rate(dispc, channel); in dispc_plane_lclk_rate()
3401 static void dispc_dump_clocks_channel(struct dispc_device *dispc, in dispc_dump_clocks_channel() argument
3410 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3415 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); in dispc_dump_clocks_channel()
3418 dispc_mgr_lclk_rate(dispc, channel), lcd); in dispc_dump_clocks_channel()
3420 dispc_mgr_pclk_rate(dispc, channel), pcd); in dispc_dump_clocks_channel()
3423 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) in dispc_dump_clocks() argument
3429 if (dispc_runtime_get(dispc)) in dispc_dump_clocks()
3434 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3438 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3440 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in dispc_dump_clocks()
3442 l = dispc_read_reg(dispc, DISPC_DIVISOR); in dispc_dump_clocks()
3446 (dispc_fclk_rate(dispc)/lcd), lcd); in dispc_dump_clocks()
3449 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); in dispc_dump_clocks()
3451 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_dump_clocks()
3452 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); in dispc_dump_clocks()
3453 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_dump_clocks()
3454 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); in dispc_dump_clocks()
3456 dispc_runtime_put(dispc); in dispc_dump_clocks()
3461 struct dispc_device *dispc = s->private; in dispc_dump_regs() local
3478 #define DUMPREG(dispc, r) \ in dispc_dump_regs() argument
3479 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3481 if (dispc_runtime_get(dispc)) in dispc_dump_regs()
3485 DUMPREG(dispc, DISPC_REVISION); in dispc_dump_regs()
3486 DUMPREG(dispc, DISPC_SYSCONFIG); in dispc_dump_regs()
3487 DUMPREG(dispc, DISPC_SYSSTATUS); in dispc_dump_regs()
3488 DUMPREG(dispc, DISPC_IRQSTATUS); in dispc_dump_regs()
3489 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3490 DUMPREG(dispc, DISPC_CONTROL); in dispc_dump_regs()
3491 DUMPREG(dispc, DISPC_CONFIG); in dispc_dump_regs()
3492 DUMPREG(dispc, DISPC_CAPABLE); in dispc_dump_regs()
3493 DUMPREG(dispc, DISPC_LINE_STATUS); in dispc_dump_regs()
3494 DUMPREG(dispc, DISPC_LINE_NUMBER); in dispc_dump_regs()
3495 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_dump_regs()
3496 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_dump_regs()
3497 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); in dispc_dump_regs()
3498 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_dump_regs()
3499 DUMPREG(dispc, DISPC_CONTROL2); in dispc_dump_regs()
3500 DUMPREG(dispc, DISPC_CONFIG2); in dispc_dump_regs()
3502 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_dump_regs()
3503 DUMPREG(dispc, DISPC_CONTROL3); in dispc_dump_regs()
3504 DUMPREG(dispc, DISPC_CONFIG3); in dispc_dump_regs()
3506 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3507 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); in dispc_dump_regs()
3512 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ in dispc_dump_regs() argument
3514 dispc_read_reg(dispc, DISPC_REG(i, r))) in dispc_dump_regs()
3519 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_dump_regs()
3520 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); in dispc_dump_regs()
3521 DUMPREG(dispc, i, DISPC_TRANS_COLOR); in dispc_dump_regs()
3522 DUMPREG(dispc, i, DISPC_SIZE_MGR); in dispc_dump_regs()
3527 DUMPREG(dispc, i, DISPC_TIMING_H); in dispc_dump_regs()
3528 DUMPREG(dispc, i, DISPC_TIMING_V); in dispc_dump_regs()
3529 DUMPREG(dispc, i, DISPC_POL_FREQ); in dispc_dump_regs()
3530 DUMPREG(dispc, i, DISPC_DIVISORo); in dispc_dump_regs()
3532 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); in dispc_dump_regs()
3533 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); in dispc_dump_regs()
3534 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); in dispc_dump_regs()
3536 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_dump_regs()
3537 DUMPREG(dispc, i, DISPC_CPR_COEF_R); in dispc_dump_regs()
3538 DUMPREG(dispc, i, DISPC_CPR_COEF_G); in dispc_dump_regs()
3539 DUMPREG(dispc, i, DISPC_CPR_COEF_B); in dispc_dump_regs()
3545 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3546 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3547 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3548 DUMPREG(dispc, i, DISPC_OVL_POSITION); in dispc_dump_regs()
3549 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3550 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3551 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3552 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3553 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3554 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3556 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_dump_regs()
3557 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); in dispc_dump_regs()
3558 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3559 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3562 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); in dispc_dump_regs()
3563 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); in dispc_dump_regs()
3567 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3568 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3569 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3570 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3571 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3572 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3573 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3574 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3575 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3576 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3578 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3579 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3582 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3584 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3585 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3586 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3587 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3588 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3589 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3590 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3591 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3593 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3594 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3596 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3597 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3598 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3599 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3600 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3601 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3602 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3603 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3604 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3605 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3607 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3608 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3615 #define DUMPREG(dispc, plane, name, i) \ in dispc_dump_regs() argument
3618 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) in dispc_dump_regs()
3623 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3625 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); in dispc_dump_regs()
3628 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); in dispc_dump_regs()
3631 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); in dispc_dump_regs()
3633 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_dump_regs()
3635 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); in dispc_dump_regs()
3638 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3640 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); in dispc_dump_regs()
3643 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); in dispc_dump_regs()
3646 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); in dispc_dump_regs()
3650 dispc_runtime_put(dispc); in dispc_dump_regs()
3659 int dispc_calc_clock_rates(struct dispc_device *dispc, in dispc_calc_clock_rates() argument
3674 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, in dispc_div_calc() argument
3692 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3695 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3718 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_div_calc()
3719 fck = dispc_core_clk_rate(dispc); in dispc_div_calc()
3734 void dispc_mgr_set_clock_div(struct dispc_device *dispc, in dispc_mgr_set_clock_div() argument
3741 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3745 int dispc_mgr_get_clock_div(struct dispc_device *dispc, in dispc_mgr_get_clock_div() argument
3751 fck = dispc_fclk_rate(dispc); in dispc_mgr_get_clock_div()
3753 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3754 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3762 u32 dispc_read_irqstatus(struct dispc_device *dispc) in dispc_read_irqstatus() argument
3764 return dispc_read_reg(dispc, DISPC_IRQSTATUS); in dispc_read_irqstatus()
3767 void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) in dispc_clear_irqstatus() argument
3769 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); in dispc_clear_irqstatus()
3772 void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) in dispc_write_irqenable() argument
3774 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3777 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_write_irqenable()
3779 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); in dispc_write_irqenable()
3782 dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3785 void dispc_enable_sidle(struct dispc_device *dispc) in dispc_enable_sidle() argument
3788 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); in dispc_enable_sidle()
3791 void dispc_disable_sidle(struct dispc_device *dispc) in dispc_disable_sidle() argument
3793 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ in dispc_disable_sidle()
3796 u32 dispc_mgr_gamma_size(struct dispc_device *dispc, in dispc_mgr_gamma_size() argument
3801 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3807 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, in dispc_mgr_write_gamma_table() argument
3811 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3824 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3828 static void dispc_restore_gamma_tables(struct dispc_device *dispc) in dispc_restore_gamma_tables() argument
3832 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3835 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); in dispc_restore_gamma_tables()
3837 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); in dispc_restore_gamma_tables()
3839 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_gamma_tables()
3840 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); in dispc_restore_gamma_tables()
3842 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_gamma_tables()
3843 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); in dispc_restore_gamma_tables()
3851 void dispc_mgr_set_gamma(struct dispc_device *dispc, in dispc_mgr_set_gamma() argument
3857 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3863 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3895 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3896 dispc_mgr_write_gamma_table(dispc, channel); in dispc_mgr_set_gamma()
3899 static int dispc_init_gamma_tables(struct dispc_device *dispc) in dispc_init_gamma_tables() argument
3903 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3906 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3911 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_init_gamma_tables()
3915 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_init_gamma_tables()
3918 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3923 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3925 dispc_mgr_set_gamma(dispc, channel, NULL, 0); in dispc_init_gamma_tables()
3930 static void _omap_dispc_initial_config(struct dispc_device *dispc) in _omap_dispc_initial_config() argument
3935 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in _omap_dispc_initial_config()
3936 l = dispc_read_reg(dispc, DISPC_DIVISOR); in _omap_dispc_initial_config()
3940 dispc_write_reg(dispc, DISPC_DIVISOR, l); in _omap_dispc_initial_config()
3942 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3946 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3947 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); in _omap_dispc_initial_config()
3953 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || in _omap_dispc_initial_config()
3954 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3955 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
3957 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); in _omap_dispc_initial_config()
3959 dispc_init_fifos(dispc); in _omap_dispc_initial_config()
3961 dispc_configure_burst_sizes(dispc); in _omap_dispc_initial_config()
3963 dispc_ovl_enable_zorder_planes(dispc); in _omap_dispc_initial_config()
3965 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
3966 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); in _omap_dispc_initial_config()
3968 if (dispc_has_feature(dispc, FEAT_MFLAG)) in _omap_dispc_initial_config()
3969 dispc_init_mflag(dispc); in _omap_dispc_initial_config()
4513 struct dispc_device *dispc = arg; in dispc_irq_handler() local
4515 if (!dispc->is_enabled) in dispc_irq_handler()
4518 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4521 int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, in dispc_request_irq() argument
4526 if (dispc->user_handler != NULL) in dispc_request_irq()
4529 dispc->user_handler = handler; in dispc_request_irq()
4530 dispc->user_data = dev_id; in dispc_request_irq()
4535 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4536 IRQF_SHARED, "OMAP DISPC", dispc); in dispc_request_irq()
4538 dispc->user_handler = NULL; in dispc_request_irq()
4539 dispc->user_data = NULL; in dispc_request_irq()
4545 void dispc_free_irq(struct dispc_device *dispc, void *dev_id) in dispc_free_irq() argument
4547 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4549 dispc->user_handler = NULL; in dispc_free_irq()
4550 dispc->user_data = NULL; in dispc_free_irq()
4553 u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) in dispc_get_memory_bandwidth_limit() argument
4558 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4635 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) in dispc_errata_i734_wa_init() argument
4637 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4643 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4646 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4654 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) in dispc_errata_i734_wa_fini() argument
4656 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4659 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4663 static void dispc_errata_i734_wa(struct dispc_device *dispc) in dispc_errata_i734_wa() argument
4665 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, in dispc_errata_i734_wa()
4672 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4675 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); in dispc_errata_i734_wa()
4682 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); in dispc_errata_i734_wa()
4685 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, in dispc_errata_i734_wa()
4687 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); in dispc_errata_i734_wa()
4690 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); in dispc_errata_i734_wa()
4691 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4693 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); in dispc_errata_i734_wa()
4694 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); in dispc_errata_i734_wa()
4696 dispc_clear_irqstatus(dispc, framedone_irq); in dispc_errata_i734_wa()
4699 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); in dispc_errata_i734_wa()
4700 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); in dispc_errata_i734_wa()
4707 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { in dispc_errata_i734_wa()
4709 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4714 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); in dispc_errata_i734_wa()
4717 dispc_clear_irqstatus(dispc, 0xffffffff); in dispc_errata_i734_wa()
4720 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); in dispc_errata_i734_wa()
4747 struct dispc_device *dispc; in dispc_bind() local
4752 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); in dispc_bind()
4753 if (!dispc) in dispc_bind()
4756 dispc->pdev = pdev; in dispc_bind()
4757 platform_set_drvdata(pdev, dispc); in dispc_bind()
4758 dispc->dss = dss; in dispc_bind()
4766 dispc->feat = soc->data; in dispc_bind()
4768 dispc->feat = device_get_match_data(&pdev->dev); in dispc_bind()
4770 r = dispc_errata_i734_wa_init(dispc); in dispc_bind()
4774 dispc->base = devm_platform_ioremap_resource(pdev, 0); in dispc_bind()
4775 if (IS_ERR(dispc->base)) { in dispc_bind()
4776 r = PTR_ERR(dispc->base); in dispc_bind()
4780 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4781 if (dispc->irq < 0) { in dispc_bind()
4788 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4789 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4791 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4796 &dispc->syscon_pol_offset)) { in dispc_bind()
4803 r = dispc_init_gamma_tables(dispc); in dispc_bind()
4809 r = dispc_runtime_get(dispc); in dispc_bind()
4813 _omap_dispc_initial_config(dispc); in dispc_bind()
4815 rev = dispc_read_reg(dispc, DISPC_REVISION); in dispc_bind()
4819 dispc_runtime_put(dispc); in dispc_bind()
4821 dss->dispc = dispc; in dispc_bind()
4823 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4824 dispc); in dispc_bind()
4831 kfree(dispc); in dispc_bind()
4837 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_unbind() local
4838 struct dss_device *dss = dispc->dss; in dispc_unbind()
4840 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4842 dss->dispc = NULL; in dispc_unbind()
4846 dispc_errata_i734_wa_fini(dispc); in dispc_unbind()
4848 kfree(dispc); in dispc_unbind()
4868 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_suspend() local
4870 dispc->is_enabled = false; in dispc_runtime_suspend()
4874 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4876 dispc_save_context(dispc); in dispc_runtime_suspend()
4883 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_resume() local
4891 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { in dispc_runtime_resume()
4892 _omap_dispc_initial_config(dispc); in dispc_runtime_resume()
4894 dispc_errata_i734_wa(dispc); in dispc_runtime_resume()
4896 dispc_restore_context(dispc); in dispc_runtime_resume()
4898 dispc_restore_gamma_tables(dispc); in dispc_runtime_resume()
4901 dispc->is_enabled = true; in dispc_runtime_resume()