subdev/therm/gk104.c

38 	for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {  in gk104_clkgate_enable()
42 		nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500);  in gk104_clkgate_enable()
46 	nvkm_wr32(dev, 0x020288, therm->idle_filter->fecs);  in gk104_clkgate_enable()
47 	nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu);  in gk104_clkgate_enable()
50 	for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {  in gk104_clkgate_enable()
54 		nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045);  in gk104_clkgate_enable()
67 	for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {  in gk104_clkgate_fini()
71 		nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54);  in gk104_clkgate_fini()
76 	{ NVKM_ENGINE_GR,     0, 0x00 },
77 	{ NVKM_ENGINE_MSPDEC, 0, 0x04 },
78 	{ NVKM_ENGINE_MSPPP,  0, 0x08 },
79 	{ NVKM_ENGINE_MSVLD,  0, 0x0c },
80 	{ NVKM_ENGINE_CE,     0, 0x10 },
81 	{ NVKM_ENGINE_CE,     1, 0x14 },
82 	{ NVKM_ENGINE_MSENC,  0, 0x18 },
83 	{ NVKM_ENGINE_CE,     2, 0x1c },
88 	.fecs = 0x00001000,
89 	.hubmmu = 0x00001000,
124 	return 0;  in gk104_therm_new_()