Lines Matching +full:0 +full:x003fffff

30 	u32 pteo = (ptei << 2) & ~0x0000000f;  in nv44_vmm_pgt_fill()
33 tmp[0] = nvkm_ro32(pt->memory, pteo + 0x0); in nv44_vmm_pgt_fill()
34 tmp[1] = nvkm_ro32(pt->memory, pteo + 0x4); in nv44_vmm_pgt_fill()
35 tmp[2] = nvkm_ro32(pt->memory, pteo + 0x8); in nv44_vmm_pgt_fill()
36 tmp[3] = nvkm_ro32(pt->memory, pteo + 0xc); in nv44_vmm_pgt_fill()
40 switch (ptei++ & 0x3) { in nv44_vmm_pgt_fill()
41 case 0: in nv44_vmm_pgt_fill()
42 tmp[0] &= ~0x07ffffff; in nv44_vmm_pgt_fill()
43 tmp[0] |= addr; in nv44_vmm_pgt_fill()
46 tmp[0] &= ~0xf8000000; in nv44_vmm_pgt_fill()
47 tmp[0] |= addr << 27; in nv44_vmm_pgt_fill()
48 tmp[1] &= ~0x003fffff; in nv44_vmm_pgt_fill()
52 tmp[1] &= ~0xffc00000; in nv44_vmm_pgt_fill()
54 tmp[2] &= ~0x0001ffff; in nv44_vmm_pgt_fill()
58 tmp[2] &= ~0xfffe0000; in nv44_vmm_pgt_fill()
60 tmp[3] &= ~0x00000fff; in nv44_vmm_pgt_fill()
66 VMM_WO032(pt, vmm, pteo + 0x0, tmp[0]); in nv44_vmm_pgt_fill()
67 VMM_WO032(pt, vmm, pteo + 0x4, tmp[1]); in nv44_vmm_pgt_fill()
68 VMM_WO032(pt, vmm, pteo + 0x8, tmp[2]); in nv44_vmm_pgt_fill()
69 VMM_WO032(pt, vmm, pteo + 0xc, tmp[3] | 0x40000000); in nv44_vmm_pgt_fill()
80 for (i = 0; i < pten; i++, addr += 0x1000) in nv44_vmm_pgt_pte()
88 for (i = 0; i < 4; i++, addr += 0x1000) in nv44_vmm_pgt_pte()
90 VMM_WO032(pt, vmm, ptei++ * 4, tmp[0] >> 0 | tmp[1] << 27); in nv44_vmm_pgt_pte()
93 VMM_WO032(pt, vmm, ptei++ * 4, tmp[3] >> 15 | 0x40000000); in nv44_vmm_pgt_pte()
98 for (i = 0; i < ptes; i++, addr += 0x1000) in nv44_vmm_pgt_pte()
127 for (i = 0; i < 4; i++) in nv44_vmm_pgt_dma()
129 VMM_WO032(pt, vmm, ptei++ * 4, tmp[0] >> 0 | tmp[1] << 27); in nv44_vmm_pgt_dma()
132 VMM_WO032(pt, vmm, ptei++ * 4, tmp[3] >> 15 | 0x40000000); in nv44_vmm_pgt_dma()
159 VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000); in nv44_vmm_pgt_unmap()
160 VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000); in nv44_vmm_pgt_unmap()
161 VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000); in nv44_vmm_pgt_unmap()
162 VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000); in nv44_vmm_pgt_unmap()
180 { PGT, 17, 4, 0x80000, &nv44_vmm_desc_pgt },
188 nvkm_wr32(device, 0x100814, vmm->limit - 4096); in nv44_vmm_flush()
189 nvkm_wr32(device, 0x100808, 0x000000020); in nv44_vmm_flush()
191 if (nvkm_rd32(device, 0x100808) & 0x00000001) in nv44_vmm_flush()
194 nvkm_wr32(device, 0x100808, 0x00000000); in nv44_vmm_flush()
202 { 12, &nv44_vmm_desc_12[0], NVKM_VMM_PAGE_HOST },
216 ret = nv04_vmm_new_(&nv44_vmm, mmu, 0, managed, addr, size, in nv44_vmm_new()
226 vmm->null = 0; in nv44_vmm_new()
229 return 0; in nv44_vmm_new()