Lines Matching refs:CWL
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
100 T(CWL) << 8 | in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
105 max_t(s8, T(CWL) - 2, 1) << 8 | in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
112 (T(WTR) + 1 + T(CWL)) << 8 | in nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
167 T(CWL) = T(CL) - 1; in nv50_ram_timing_read()
170 T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; in nv50_ram_timing_read()
176 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()