Lines Matching +full:1000 +full:base +full:- +full:t
25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
157 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_link_train()
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
159 struct nvkm_device *device = subdev->device; in gt215_link_train()
160 struct nvkm_bios *bios = device->bios; in gt215_link_train()
161 struct nvkm_clk *clk = device->clk; in gt215_link_train()
170 if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true) in gt215_link_train()
171 return -ENOSYS; in gt215_link_train()
176 return -ENOMEM; in gt215_link_train()
178 train->state = NVA3_TRAIN_EXEC; in gt215_link_train()
184 return -ENOENT; in gt215_link_train()
194 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); in gt215_link_train()
223 ram_wr32(fuc, 0x100720, train->r_100720); in gt215_link_train()
224 ram_wr32(fuc, 0x1111e0, train->r_1111e0); in gt215_link_train()
225 ram_wr32(fuc, 0x111400, train->r_111400); in gt215_link_train()
228 ram_nsec(fuc, 1000); in gt215_link_train()
237 ram->base.func->calc(&ram->base, clk_current); in gt215_link_train()
240 /* Post-processing, avoids flicker */ in gt215_link_train()
246 ram_train_result(ram->base.fb, result, 64); in gt215_link_train()
251 nvkm_debug(subdev, "Train: %08x %08x %08x", train->r_100720, in gt215_link_train()
252 train->r_1111e0, train->r_111400); in gt215_link_train()
256 train->state = NVA3_TRAIN_DONE; in gt215_link_train()
261 if(ret == -EBUSY) in gt215_link_train()
264 train->state = NVA3_TRAIN_UNSUPPORTED; in gt215_link_train()
280 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train_init()
281 struct nvkm_device *device = ram->base.fb->subdev.device; in gt215_link_train_init()
282 struct nvkm_bios *bios = device->bios; in gt215_link_train_init()
289 train->state = NVA3_TRAIN_UNSUPPORTED; in gt215_link_train_init()
294 return -ENOENT; in gt215_link_train_init()
299 train->state = NVA3_TRAIN_ONCE; in gt215_link_train_init()
302 true, true, &ram->ltrain.memory); in gt215_link_train_init()
306 addr = nvkm_memory_addr(ram->ltrain.memory); in gt215_link_train_init()
331 train->r_100720 = nvkm_rd32(device, 0x100720); in gt215_link_train_init()
332 train->r_1111e0 = nvkm_rd32(device, 0x1111e0); in gt215_link_train_init()
333 train->r_111400 = nvkm_rd32(device, 0x111400); in gt215_link_train_init()
340 nvkm_memory_unref(&ram->ltrain.memory); in gt215_link_train_fini()
346 #define T(t) cfg->timing_10_##t macro
350 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in gt215_ram_timing_calc()
351 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_ram_timing_calc()
352 struct nvkm_device *device = subdev->device; in gt215_ram_timing_calc()
362 switch ((!T(CWL)) * ram->base.type) { in gt215_ram_timing_calc()
364 T(CWL) = T(CL) - 1; in gt215_ram_timing_calc()
367 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in gt215_ram_timing_calc()
372 tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL; in gt215_ram_timing_calc()
374 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
376 max_t(u8,T(18), 1) << 16 | in gt215_ram_timing_calc()
377 (T(WTR) + 1 + T(CWL)) << 8 | in gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
379 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
380 (T(RRD) << 16) | in gt215_ram_timing_calc()
381 (T(RCDWR) << 8) | in gt215_ram_timing_calc()
382 T(RCDRD); in gt215_ram_timing_calc()
384 (0x30 + T(CL)) << 24 | in gt215_ram_timing_calc()
385 (0xb + T(CL)) << 8 | in gt215_ram_timing_calc()
386 (T(CL) - 1); in gt215_ram_timing_calc()
387 timing[4] = T(20) << 24 | in gt215_ram_timing_calc()
388 T(21) << 16 | in gt215_ram_timing_calc()
389 T(13) << 8 | in gt215_ram_timing_calc()
390 T(13); in gt215_ram_timing_calc()
391 timing[5] = T(RFC) << 24 | in gt215_ram_timing_calc()
392 max_t(u8,T(RCDRD), T(RCDWR)) << 16 | in gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | in gt215_ram_timing_calc()
394 T(RP); in gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | in gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
399 ((tUNK_base + T(CL)) << 16) | in gt215_ram_timing_calc()
403 switch (ram->base.type) { in gt215_ram_timing_calc()
406 tUNK_40_0 = prevCL - (cur8 & 0xff); in gt215_ram_timing_calc()
408 timing[8] |= T(CL); in gt215_ram_timing_calc()
421 #undef T
427 ram_nsec(fuc, 1000); in nvkm_sddr2_dll_reset()
429 ram_nsec(fuc, 1000); in nvkm_sddr2_dll_reset()
440 ram_nsec(fuc, 1000); in nvkm_sddr3_dll_disable()
451 ram_nsec(fuc, 1000); in nvkm_gddr3_dll_disable()
458 ram_wr32(fuc, 0x004004, mclk->pll); in gt215_ram_lock_pll()
468 struct nvkm_gpio *gpio = fuc->base.fb->subdev.device->gpio; in gt215_ram_gpio()
492 gt215_ram_calc(struct nvkm_ram *base, u32 freq) in gt215_ram_calc() argument
494 struct gt215_ram *ram = gt215_ram(base); in gt215_ram_calc()
495 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_ram_calc()
496 struct gt215_ltrain *train = &ram->ltrain; in gt215_ram_calc()
497 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_ram_calc()
498 struct nvkm_device *device = subdev->device; in gt215_ram_calc()
499 struct nvkm_bios *bios = device->bios; in gt215_ram_calc()
501 struct nvkm_gpio *gpio = device->gpio; in gt215_ram_calc()
511 next = &ram->base.target; in gt215_ram_calc()
512 next->freq = freq; in gt215_ram_calc()
513 ram->base.next = next; in gt215_ram_calc()
515 if (ram->ltrain.state == NVA3_TRAIN_ONCE) in gt215_ram_calc()
519 data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len, in gt215_ram_calc()
520 &next->bios); in gt215_ram_calc()
523 return -EINVAL; in gt215_ram_calc()
530 return -EINVAL; in gt215_ram_calc()
534 &ver, &hdr, &next->bios); in gt215_ram_calc()
537 return -EINVAL; in gt215_ram_calc()
541 if (next->bios.ramcfg_timing != 0xff) { in gt215_ram_calc()
542 data = nvbios_timingEp(bios, next->bios.ramcfg_timing, in gt215_ram_calc()
544 &next->bios); in gt215_ram_calc()
547 return -EINVAL; in gt215_ram_calc()
551 ret = gt215_pll_info(device->clk, 0x12, 0x4000, freq, &mclk); in gt215_ram_calc()
559 ret = ram_init(fuc, ram->base.fb); in gt215_ram_calc()
563 /* Determine ram-specific MR values */ in gt215_ram_calc()
564 ram->base.mr[0] = ram_rd32(fuc, mr[0]); in gt215_ram_calc()
565 ram->base.mr[1] = ram_rd32(fuc, mr[1]); in gt215_ram_calc()
566 ram->base.mr[2] = ram_rd32(fuc, mr[2]); in gt215_ram_calc()
568 switch (ram->base.type) { in gt215_ram_calc()
570 ret = nvkm_sddr2_calc(&ram->base); in gt215_ram_calc()
573 ret = nvkm_sddr3_calc(&ram->base); in gt215_ram_calc()
576 ret = nvkm_gddr3_calc(&ram->base); in gt215_ram_calc()
579 ret = -ENOSYS; in gt215_ram_calc()
597 if (!next->bios.ramcfg_DLLoff) in gt215_ram_calc()
605 if (next->bios.ramcfg_10_02_10) { in gt215_ram_calc()
614 /* If switching from non-pll to pll, lock before disabling FB */ in gt215_ram_calc()
629 if (!next->bios.ramcfg_10_02_10) { in gt215_ram_calc()
630 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) in gt215_ram_calc()
637 switch (next->bios.ramcfg_DLLoff * ram->base.type) { in gt215_ram_calc()
639 nvkm_sddr3_dll_disable(fuc, ram->base.mr); in gt215_ram_calc()
642 nvkm_gddr3_dll_disable(fuc, ram->base.mr); in gt215_ram_calc()
646 if (next->bios.timing_10_ODT) in gt215_ram_calc()
657 if (device->chipset == 0xa3 && freq <= 500000) in gt215_ram_calc()
663 next->bios.ramcfg_FBVDDQ) { in gt215_ram_calc()
671 gt215_ram_gpio(fuc, 0x18, !next->bios.ramcfg_FBVDDQ); in gt215_ram_calc()
679 * pll->pll: first switch to a 324MHz clock, set up new PLL, switch in gt215_ram_calc()
680 * clk->pll: Set up new PLL, switch in gt215_ram_calc()
681 * pll->clk: Set up clock, switch in gt215_ram_calc()
682 * clk->clk: Overwrite ctrl and other bits, switch */ in gt215_ram_calc()
684 /* Switch to regular clock - 324MHz */ in gt215_ram_calc()
707 if (next->bios.rammap_10_04_08) { in gt215_ram_calc()
708 ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 | in gt215_ram_calc()
709 next->bios.ramcfg_10_05 << 8 | in gt215_ram_calc()
710 next->bios.ramcfg_10_05); in gt215_ram_calc()
711 ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 | in gt215_ram_calc()
712 next->bios.ramcfg_10_07); in gt215_ram_calc()
713 ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 | in gt215_ram_calc()
714 next->bios.ramcfg_10_03_0f << 16 | in gt215_ram_calc()
715 next->bios.ramcfg_10_09_0f | in gt215_ram_calc()
719 if (train->state == NVA3_TRAIN_DONE) { in gt215_ram_calc()
721 ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400); in gt215_ram_calc()
722 ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0); in gt215_ram_calc()
723 ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720); in gt215_ram_calc()
732 if (device->chipset == 0xa3 && freq > 500000) { in gt215_ram_calc()
748 for (i = 2; i >= 0; i--) { in gt215_ram_calc()
749 if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) { in gt215_ram_calc()
750 ram_wr32(fuc, mr[i], ram->base.mr[i]); in gt215_ram_calc()
751 ram_nsec(fuc, 1000); in gt215_ram_calc()
766 ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12); in gt215_ram_calc()
775 if (device->chipset == 0xa8) { in gt215_ram_calc()
777 if (!next->bios.ramcfg_10_02_04) in gt215_ram_calc()
780 if (next->bios.ramcfg_10_02_04) { in gt215_ram_calc()
781 switch (ram->base.type) { in gt215_ram_calc()
785 if (next->bios.ramcfg_10_02_10) in gt215_ram_calc()
794 switch (ram->base.type) { in gt215_ram_calc()
800 if (next->bios.ramcfg_10_02_10) in gt215_ram_calc()
814 unk714 |= (next->bios.ramcfg_10_04_01) << 8; in gt215_ram_calc()
816 if (next->bios.ramcfg_10_02_20) in gt215_ram_calc()
818 if (next->bios.ramcfg_10_02_02) in gt215_ram_calc()
820 if (next->bios.ramcfg_10_02_01) in gt215_ram_calc()
822 if (next->bios.timing_10_24 != 0xff) { in gt215_ram_calc()
824 unk718 |= next->bios.timing_10_24 << 28; in gt215_ram_calc()
826 if (next->bios.ramcfg_10_02_10) in gt215_ram_calc()
834 if (!next->bios.timing_10_ODT) in gt215_ram_calc()
838 if (!next->bios.ramcfg_DLLoff) in gt215_ram_calc()
841 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { in gt215_ram_calc()
847 if (ram->base.type == NVKM_RAM_TYPE_DDR3) { in gt215_ram_calc()
856 /* Re-enable FB */ in gt215_ram_calc()
861 if (next->bios.rammap_10_04_02) in gt215_ram_calc()
863 if (next->bios.ramcfg_10_02_10) { in gt215_ram_calc()
883 gt215_ram_prog(struct nvkm_ram *base) in gt215_ram_prog() argument
885 struct gt215_ram *ram = gt215_ram(base); in gt215_ram_prog()
886 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_ram_prog()
887 struct nvkm_device *device = ram->base.fb->subdev.device; in gt215_ram_prog()
888 bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true); in gt215_ram_prog()
895 /* Post-processing, avoids flicker */ in gt215_ram_prog()
908 gt215_ram_tidy(struct nvkm_ram *base) in gt215_ram_tidy() argument
910 struct gt215_ram *ram = gt215_ram(base); in gt215_ram_tidy()
911 ram_exec(&ram->fuc, false); in gt215_ram_tidy()
915 gt215_ram_init(struct nvkm_ram *base) in gt215_ram_init() argument
917 struct gt215_ram *ram = gt215_ram(base); in gt215_ram_init()
923 gt215_ram_dtor(struct nvkm_ram *base) in gt215_ram_dtor() argument
925 struct gt215_ram *ram = gt215_ram(base); in gt215_ram_dtor()
946 return -ENOMEM; in gt215_ram_new()
947 *pram = &ram->base; in gt215_ram_new()
949 ret = nv50_ram_ctor(>215_ram_func, fb, &ram->base); in gt215_ram_new()
953 ram->fuc.r_0x001610 = ramfuc_reg(0x001610); in gt215_ram_new()
954 ram->fuc.r_0x001700 = ramfuc_reg(0x001700); in gt215_ram_new()
955 ram->fuc.r_0x002504 = ramfuc_reg(0x002504); in gt215_ram_new()
956 ram->fuc.r_0x004000 = ramfuc_reg(0x004000); in gt215_ram_new()
957 ram->fuc.r_0x004004 = ramfuc_reg(0x004004); in gt215_ram_new()
958 ram->fuc.r_0x004018 = ramfuc_reg(0x004018); in gt215_ram_new()
959 ram->fuc.r_0x004128 = ramfuc_reg(0x004128); in gt215_ram_new()
960 ram->fuc.r_0x004168 = ramfuc_reg(0x004168); in gt215_ram_new()
961 ram->fuc.r_0x100080 = ramfuc_reg(0x100080); in gt215_ram_new()
962 ram->fuc.r_0x100200 = ramfuc_reg(0x100200); in gt215_ram_new()
963 ram->fuc.r_0x100210 = ramfuc_reg(0x100210); in gt215_ram_new()
965 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4)); in gt215_ram_new()
966 ram->fuc.r_0x100264 = ramfuc_reg(0x100264); in gt215_ram_new()
967 ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0); in gt215_ram_new()
968 ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4); in gt215_ram_new()
969 ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc); in gt215_ram_new()
970 ram->fuc.r_0x10053c = ramfuc_reg(0x10053c); in gt215_ram_new()
971 ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0); in gt215_ram_new()
972 ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4); in gt215_ram_new()
973 ram->fuc.r_0x100700 = ramfuc_reg(0x100700); in gt215_ram_new()
974 ram->fuc.r_0x100714 = ramfuc_reg(0x100714); in gt215_ram_new()
975 ram->fuc.r_0x100718 = ramfuc_reg(0x100718); in gt215_ram_new()
976 ram->fuc.r_0x10071c = ramfuc_reg(0x10071c); in gt215_ram_new()
977 ram->fuc.r_0x100720 = ramfuc_reg(0x100720); in gt215_ram_new()
978 ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask); in gt215_ram_new()
979 ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask); in gt215_ram_new()
980 ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask); in gt215_ram_new()
981 ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask); in gt215_ram_new()
982 ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804); in gt215_ram_new()
983 ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask); in gt215_ram_new()
984 ram->fuc.r_0x111100 = ramfuc_reg(0x111100); in gt215_ram_new()
985 ram->fuc.r_0x111104 = ramfuc_reg(0x111104); in gt215_ram_new()
986 ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0); in gt215_ram_new()
987 ram->fuc.r_0x111400 = ramfuc_reg(0x111400); in gt215_ram_new()
988 ram->fuc.r_0x611200 = ramfuc_reg(0x611200); in gt215_ram_new()
990 if (ram->base.ranks > 1) { in gt215_ram_new()
991 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8); in gt215_ram_new()
992 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc); in gt215_ram_new()
993 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8); in gt215_ram_new()
994 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec); in gt215_ram_new()
996 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0); in gt215_ram_new()
997 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4); in gt215_ram_new()
998 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0); in gt215_ram_new()
999 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4); in gt215_ram_new()
1001 ram->fuc.r_gpio[0] = ramfuc_reg(0x00e104); in gt215_ram_new()
1002 ram->fuc.r_gpio[1] = ramfuc_reg(0x00e108); in gt215_ram_new()
1003 ram->fuc.r_gpio[2] = ramfuc_reg(0x00e120); in gt215_ram_new()
1004 ram->fuc.r_gpio[3] = ramfuc_reg(0x00e124); in gt215_ram_new()