38 		{ 0x24, 0x00 },  in nv05_devinit_meminit()
39 		{ 0x28, 0x00 },  in nv05_devinit_meminit()
40 		{ 0x24, 0x01 },  in nv05_devinit_meminit()
41 		{ 0x1f, 0x00 },  in nv05_devinit_meminit()
42 		{ 0x0f, 0x00 },  in nv05_devinit_meminit()
43 		{ 0x17, 0x00 },  in nv05_devinit_meminit()
44 		{ 0x06, 0x00 },  in nv05_devinit_meminit()
45 		{ 0x00, 0x00 }  in nv05_devinit_meminit()
51 	u32 patt = 0xdeadbeef;  in nv05_devinit_meminit()
63 	strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;  in nv05_devinit_meminit()
65 		ramcfg[0] = nvbios_rd08(bios, data + 2 * strap + 0);  in nv05_devinit_meminit()
68 		ramcfg[0] = default_config_tab[strap][0];  in nv05_devinit_meminit()
73 	nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);  in nv05_devinit_meminit()
78 	nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);  in nv05_devinit_meminit()
82 		for (i = 0, data += 0x10; i < 8; i++, data += 4) {  in nv05_devinit_meminit()
89 	nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);  in nv05_devinit_meminit()
91 	if (ramcfg[1] & 0x80)  in nv05_devinit_meminit()
92 		nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);  in nv05_devinit_meminit()
94 	nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);  in nv05_devinit_meminit()
95 	nvkm_mask(device, NV04_PFB_CFG1, 0, 1);  in nv05_devinit_meminit()
98 	for (i = 0; i < 4; i++)  in nv05_devinit_meminit()
101 	if (fbmem_peek(fb, 0xc) != patt)  in nv05_devinit_meminit()
103 			  NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);  in nv05_devinit_meminit()
109 	    (!fbmem_readback(fb, 0x1000000, ++patt) ||  in nv05_devinit_meminit()
110 	     !fbmem_readback(fb, 0, ++patt)))  in nv05_devinit_meminit()
115 	    !fbmem_readback(fb, 0x800000, ++patt))  in nv05_devinit_meminit()
119 	if (!fbmem_readback(fb, 0x400000, ++patt))  in nv05_devinit_meminit()
125 	nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);  in nv05_devinit_meminit()