34 	struct nvkm_device *device = clk->base.subdev.device;  in read_div()
35 	switch (device->chipset) {  in read_div()
54 	struct nvkm_subdev *subdev = &clk->base.subdev;  in read_pll_src()
55 	struct nvkm_device *device = subdev->device;  in read_pll_src()
56 	u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_src()  local
60 	switch (device->chipset) {  in read_pll_src()
73 		coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c));  in read_pll_src()
74 		ref *=  (coef & 0x01000000) ? 2 : 4;  in read_pll_src()
75 		P    =  (coef & 0x00070000) >> 16;  in read_pll_src()
76 		N    = ((coef & 0x0000ff00) >> 8) + 1;  in read_pll_src()
77 		M    = ((coef & 0x000000ff) >> 0) + 1;  in read_pll_src()
82 		coef = nvkm_rd32(device, 0x00e81c);  in read_pll_src()
83 		P    = (coef & 0x00070000) >> 16;  in read_pll_src()
84 		N    = (coef & 0x0000ff00) >> 8;  in read_pll_src()
85 		M    = (coef & 0x000000ff) >> 0;  in read_pll_src()
103 		case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_src()
104 		case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in read_pll_src()
108 		coef =  nvkm_rd32(device, 0x00e81c + (id * 0x28));  in read_pll_src()
110 		P   += (coef & 0x00070000) >> 16;  in read_pll_src()
111 		N    = (coef & 0x0000ff00) >> 8;  in read_pll_src()
112 		M    = (coef & 0x000000ff) >> 0;  in read_pll_src()
127 	struct nvkm_subdev *subdev = &clk->base.subdev;  in read_pll_ref()
128 	struct nvkm_device *device = subdev->device;  in read_pll_ref()
129 	u32 src, mast = nvkm_rd32(device, 0x00c040);  in read_pll_ref()  local
133 		src = !!(mast & 0x00200000);  in read_pll_ref()
136 		src = !!(mast & 0x00400000);  in read_pll_ref()
139 		src = !!(mast & 0x00010000);  in read_pll_ref()
142 		src = !!(mast & 0x02000000);  in read_pll_ref()
145 		return nvkm_clk_read(&clk->base, nv_clk_src_crystal);  in read_pll_ref()
151 	if (src)  in read_pll_ref()
152 		return nvkm_clk_read(&clk->base, nv_clk_src_href);  in read_pll_ref()
160 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll()
163 	u32 coef = nvkm_rd32(device, base + 4);  in read_pll()  local
169 		/* wtf, appears to only disable post-divider on gt200 */  in read_pll()
170 		if (device->chipset != 0xa0)  in read_pll()
171 			return nvkm_clk_read(&clk->base, nv_clk_src_dom6);  in read_pll()
174 	N2 = (coef & 0xff000000) >> 24;  in read_pll()
175 	M2 = (coef & 0x00ff0000) >> 16;  in read_pll()
176 	N1 = (coef & 0x0000ff00) >> 8;  in read_pll()
177 	M1 = (coef & 0x000000ff);  in read_pll()
192 nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src)  in nv50_clk_read()  argument
195 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv50_clk_read()
196 	struct nvkm_device *device = subdev->device;  in nv50_clk_read()
200 	switch (src) {  in nv50_clk_read()
202 		return device->crystal;  in nv50_clk_read()
206 		return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);  in nv50_clk_read()
208 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;  in nv50_clk_read()
210 		return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;  in nv50_clk_read()
213 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in nv50_clk_read()
216 		case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);  in nv50_clk_read()
223 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
224 		case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);  in nv50_clk_read()
234 				return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;  in nv50_clk_read()
235 			return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
246 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
249 				return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;  in nv50_clk_read()
257 		switch (device->chipset) {  in nv50_clk_read()
266 				if (device->chipset == 0xa0) /* wtf?? */  in nv50_clk_read()
267 					return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
268 				return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;  in nv50_clk_read()
276 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
282 				return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;  in nv50_clk_read()
286 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;  in nv50_clk_read()
288 				return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;  in nv50_clk_read()
294 		switch (device->chipset) {  in nv50_clk_read()
306 			case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);  in nv50_clk_read()
308 			case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);  in nv50_clk_read()
310 				return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;  in nv50_clk_read()
321 	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);  in nv50_clk_read()
322 	return -EINVAL;  in nv50_clk_read()
328 	struct nvkm_subdev *subdev = &clk->base.subdev;  in calc_pll()
332 	ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);  in calc_pll()
345 calc_div(u32 src, u32 target, int *div)  in calc_div()  argument
347 	u32 clk0 = src, clk1 = src;  in calc_div()
356 	if (target - clk0 <= clk1 - target)  in calc_div()
358 	(*div)--;  in calc_div()
372 	struct nv50_clk_hwsq *hwsq = &clk->hwsq;  in nv50_clk_calc()
373 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv50_clk_calc()
374 	struct nvkm_device *device = subdev->device;  in nv50_clk_calc()
375 	const int shader = cstate->domain[nv_clk_src_shader];  in nv50_clk_calc()
376 	const int core = cstate->domain[nv_clk_src_core];  in nv50_clk_calc()
377 	const int vdec = cstate->domain[nv_clk_src_vdec];  in nv50_clk_calc()
378 	const int dom6 = cstate->domain[nv_clk_src_dom6];  in nv50_clk_calc()
403 		if (device->chipset != 0x98)  in nv50_clk_calc()
406 			out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);  in nv50_clk_calc()
410 		if (abs(vdec - freq) <= abs(vdec - out)) {  in nv50_clk_calc()
411 			if (device->chipset != 0x98)  in nv50_clk_calc()
427 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {  in nv50_clk_calc()
430 		if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {  in nv50_clk_calc()
433 			freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;  in nv50_clk_calc()
454 	if (device->chipset < 0x92)  in nv50_clk_calc()
462 		return -ERANGE;  in nv50_clk_calc()
474 	if (P1-- && shader == (core << 1)) {  in nv50_clk_calc()
480 			return -ERANGE;  in nv50_clk_calc()
491 	clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */  in nv50_clk_calc()
499 	return clk_exec(&clk->hwsq, true);  in nv50_clk_prog()
506 	clk_exec(&clk->hwsq, false);  in nv50_clk_tidy()
517 		return -ENOMEM;  in nv50_clk_new_()
518 	ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base);  in nv50_clk_new_()
519 	*pclk = &clk->base;  in nv50_clk_new_()
523 	clk->hwsq.r_fifo = hwsq_reg(0x002504);  in nv50_clk_new_()
524 	clk->hwsq.r_spll[0] = hwsq_reg(0x004020);  in nv50_clk_new_()
525 	clk->hwsq.r_spll[1] = hwsq_reg(0x004024);  in nv50_clk_new_()
526 	clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);  in nv50_clk_new_()
527 	clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);  in nv50_clk_new_()
528 	switch (device->chipset) {  in nv50_clk_new_()
532 		clk->hwsq.r_divs = hwsq_reg(0x004800);  in nv50_clk_new_()
535 		clk->hwsq.r_divs = hwsq_reg(0x004700);  in nv50_clk_new_()
538 	clk->hwsq.r_mast = hwsq_reg(0x00c040);  in nv50_clk_new_()