42 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll_1()
58 	struct nvkm_device *device = clk->base.subdev.device;  in read_pll_2()
60 	u32 coef = nvkm_rd32(device, reg + 0x04);  in read_pll_2()  local
61 	int N2 = (coef & 0xff000000) >> 24;  in read_pll_2()
62 	int M2 = (coef & 0x00ff0000) >> 16;  in read_pll_2()
63 	int N1 = (coef & 0x0000ff00) >> 8;  in read_pll_2()
64 	int M1 = (coef & 0x000000ff) >> 0;  in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src)  in read_clk()  argument
84 	switch (src) {  in read_clk()
97 nv40_clk_read(struct nvkm_clk *base, enum nv_clk_src src)  in nv40_clk_read()  argument
100 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv40_clk_read()
101 	struct nvkm_device *device = subdev->device;  in nv40_clk_read()
104 	switch (src) {  in nv40_clk_read()
106 		return device->crystal;  in nv40_clk_read()
119 	nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);  in nv40_clk_read()
120 	return -EINVAL;  in nv40_clk_read()
127 	struct nvkm_subdev *subdev = &clk->base.subdev;  in nv40_clk_calc_pll()
131 	ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);  in nv40_clk_calc_pll()
140 		return -ERANGE;  in nv40_clk_calc_pll()
149 	int gclk = cstate->domain[nv_clk_src_core];  in nv40_clk_calc()
150 	int sclk = cstate->domain[nv_clk_src_shader];  in nv40_clk_calc()
161 		clk->npll_ctrl = 0x80000100 | (log2P << 16);  in nv40_clk_calc()
162 		clk->npll_coef = (N1 << 8) | M1;  in nv40_clk_calc()
164 		clk->npll_ctrl = 0xc0000000 | (log2P << 16);  in nv40_clk_calc()
165 		clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;  in nv40_clk_calc()
175 		clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;  in nv40_clk_calc()
176 		clk->ctrl = 0x00000223;  in nv40_clk_calc()
178 		clk->spll = 0x00000000;  in nv40_clk_calc()
179 		clk->ctrl = 0x00000333;  in nv40_clk_calc()
189 	struct nvkm_device *device = clk->base.subdev.device;  in nv40_clk_prog()
191 	nvkm_wr32(device, 0x004004, clk->npll_coef);  in nv40_clk_prog()
192 	nvkm_mask(device, 0x004000, 0xc0070100, clk->npll_ctrl);  in nv40_clk_prog()
193 	nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll);  in nv40_clk_prog()
195 	nvkm_mask(device, 0x00c040, 0x00000333, clk->ctrl);  in nv40_clk_prog()
227 		return -ENOMEM;  in nv40_clk_new()
228 	clk->base.pll_calc = nv04_clk_pll_calc;  in nv40_clk_new()
229 	clk->base.pll_prog = nv04_clk_pll_prog;  in nv40_clk_new()
230 	*pclk = &clk->base;  in nv40_clk_new()
232 	return nvkm_clk_ctor(&nv40_clk, device, type, inst, true, &clk->base);  in nv40_clk_new()