45 	int N = (ctrl & 0x0000ff00) >> 8;  in read_pll_1()
47 	u32 ref = 27000, khz = 0;  in read_pll_1()  local
50 		khz = ref * N / M;  in read_pll_1()
52 	return khz >> P;  in read_pll_1()
63 	int N1 = (coef & 0x0000ff00) >> 8;  in read_pll_2()
66 	u32 ref = 27000, khz = 0;  in read_pll_2()  local
69 		khz = ref * N1 / M1;  in read_pll_2()
72 				khz = khz * N2 / M2;  in read_pll_2()
74 				khz = 0;  in read_pll_2()
78 	return khz >> P;  in read_pll_2()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz,  in nv40_clk_calc_pll()  argument
135 	if (khz < pll.vco1.max_freq)  in nv40_clk_calc_pll()
138 	ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);  in nv40_clk_calc_pll()
162 		clk->npll_coef = (N1 << 8) | M1;  in nv40_clk_calc()
165 		clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;  in nv40_clk_calc()
175 		clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;  in nv40_clk_calc()