Lines Matching +full:0 +full:x03000000

45 	return nvkm_rd32(device, 0x004600);  in read_div()
52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll()
55 u32 post_div = 0; in read_pll()
56 u32 clock = 0; in read_pll()
60 case 0x4020: in read_pll()
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
63 case 0x4028: in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
72 if ((ctrl & 0x80000000) && M1) { in read_pll()
86 u32 mast = nvkm_rd32(device, 0x00c054); in mcp77_clk_read()
87 u32 P = 0; in mcp77_clk_read()
99 switch (mast & 0x000c0000) { in mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
101 case 0x00040000: break; in mcp77_clk_read()
102 case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); in mcp77_clk_read()
103 case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk); in mcp77_clk_read()
107 P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; in mcp77_clk_read()
109 switch (mast & 0x00000003) { in mcp77_clk_read()
110 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; in mcp77_clk_read()
111 case 0x00000001: return 0; in mcp77_clk_read()
112 case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P; in mcp77_clk_read()
113 case 0x00000003: return read_pll(clk, 0x004028) >> P; in mcp77_clk_read()
117 if ((mast & 0x03000000) != 0x03000000) in mcp77_clk_read()
120 if ((mast & 0x00000200) == 0x00000000) in mcp77_clk_read()
123 switch (mast & 0x00000c00) { in mcp77_clk_read()
124 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); in mcp77_clk_read()
125 case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); in mcp77_clk_read()
126 case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
127 default: return 0; in mcp77_clk_read()
130 P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; in mcp77_clk_read()
131 switch (mast & 0x00000030) { in mcp77_clk_read()
132 case 0x00000000: in mcp77_clk_read()
133 if (mast & 0x00000040) in mcp77_clk_read()
136 case 0x00000010: break; in mcp77_clk_read()
137 case 0x00000020: return read_pll(clk, 0x004028) >> P; in mcp77_clk_read()
138 case 0x00000030: return read_pll(clk, 0x004020) >> P; in mcp77_clk_read()
142 return 0; in mcp77_clk_read()
144 P = (read_div(clk) & 0x00000700) >> 8; in mcp77_clk_read()
146 switch (mast & 0x00400000) { in mcp77_clk_read()
147 case 0x00400000: in mcp77_clk_read()
158 return 0; in mcp77_clk_read()
171 return 0; in calc_pll()
173 pll.vco2.max_freq = 0; in calc_pll()
176 return 0; in calc_pll()
185 for (*div = 0; *div <= 7; (*div)++) { in calc_P()
187 clk1 = clk0 << (*div ? 1 : 0); in calc_P()
207 u32 out = 0, clock = 0; in mcp77_clk_calc()
208 int N, M, P1, P2 = 0; in mcp77_clk_calc()
209 int divs = 0; in mcp77_clk_calc()
216 clock = calc_pll(clk, 0x4028, (core << 1), &N, &M, &P1); in mcp77_clk_calc()
238 out = 0; in mcp77_clk_calc()
242 clock = calc_pll(clk, 0x4020, shader, &N, &M, &P1); in mcp77_clk_calc()
292 return 0; in mcp77_clk_calc()
301 u32 pllmask = 0, mast; in mcp77_clk_prog()
304 int ret = 0; in mcp77_clk_prog()
311 mast = nvkm_mask(device, 0xc054, 0x03400e70, 0x03400640); in mcp77_clk_prog()
312 mast &= ~0x00400e73; in mcp77_clk_prog()
313 mast |= 0x03000000; in mcp77_clk_prog()
317 nvkm_mask(device, 0x4028, 0x00070000, clk->cctrl); in mcp77_clk_prog()
318 mast |= 0x00000002; in mcp77_clk_prog()
321 nvkm_wr32(device, 0x402c, clk->ccoef); in mcp77_clk_prog()
322 nvkm_wr32(device, 0x4028, 0x80000000 | clk->cctrl); in mcp77_clk_prog()
323 nvkm_wr32(device, 0x4040, clk->cpost); in mcp77_clk_prog()
324 pllmask |= (0x3 << 8); in mcp77_clk_prog()
325 mast |= 0x00000003; in mcp77_clk_prog()
334 nvkm_mask(device, 0x4020, 0x00070000, 0x00000000); in mcp77_clk_prog()
335 /* mast |= 0x00000000; */ in mcp77_clk_prog()
338 nvkm_mask(device, 0x4020, 0x00070000, clk->sctrl); in mcp77_clk_prog()
339 mast |= 0x00000020; in mcp77_clk_prog()
342 nvkm_wr32(device, 0x4024, clk->scoef); in mcp77_clk_prog()
343 nvkm_wr32(device, 0x4020, 0x80000000 | clk->sctrl); in mcp77_clk_prog()
344 nvkm_wr32(device, 0x4070, clk->spost); in mcp77_clk_prog()
345 pllmask |= (0x3 << 12); in mcp77_clk_prog()
346 mast |= 0x00000030; in mcp77_clk_prog()
354 u32 tmp = nvkm_rd32(device, 0x004080) & pllmask; in mcp77_clk_prog()
357 ) < 0) in mcp77_clk_prog()
362 mast |= 0x00400000; in mcp77_clk_prog()
365 nvkm_wr32(device, 0x4600, clk->vdiv); in mcp77_clk_prog()
368 nvkm_wr32(device, 0xc054, mast); in mcp77_clk_prog()
373 nvkm_wr32(device, 0x4040, 0x00000000); in mcp77_clk_prog()
374 nvkm_mask(device, 0x4028, 0x80000000, 0x00000000); in mcp77_clk_prog()
378 nvkm_wr32(device, 0x4070, 0x00000000); in mcp77_clk_prog()
379 nvkm_mask(device, 0x4020, 0x80000000, 0x00000000); in mcp77_clk_prog()
402 { nv_clk_src_crystal, 0xff },
403 { nv_clk_src_href , 0xff },
404 { nv_clk_src_core , 0xff, 0, "core", 1000 },
405 { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
406 { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },