187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz,  in gt215_clk_info()  argument
196 	switch (khz) {  in gt215_clk_info()
199 		return khz;  in gt215_clk_info()
202 		return khz;  in gt215_clk_info()
205 		return khz;  in gt215_clk_info()
208 		sdiv = min((sclk * 2) / khz, (u32)65);  in gt215_clk_info()
210 		diff = ((khz + 3000) - oclk);  in gt215_clk_info()
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz,  in gt215_pll_info()  argument
248 	ret = gt215_clk_info(&clk->base, idx, khz, info);  in gt215_pll_info()
249 	diff = khz - ret;  in gt215_pll_info()
263 	ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P);  in gt215_pll_info()
269 	info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);  in gt215_pll_info()
288 	u32 kHz = cstate->domain[nv_clk_src_host];  in calc_host()  local
291 	if (kHz == 277000) {  in calc_host()
299 	ret = gt215_clk_info(&clk->base, 0x1d, kHz, info);  in calc_host()