46 	u32 sctl = nvkm_rd32(device, 0x4120 + (idx * 4));  in read_vco()
48 	switch (sctl & 0x00000030) {  in read_vco()
49 	case 0x00000000:  in read_vco()
51 	case 0x00000020:  in read_vco()
52 		return read_pll(clk, 0x41, 0x00e820);  in read_vco()
53 	case 0x00000030:  in read_vco()
54 		return read_pll(clk, 0x42, 0x00e8a0);  in read_vco()
56 		return 0;  in read_vco()
66 	/* refclk for the 0xe8xx plls is a fixed frequency */  in read_clk()
67 	if (idx >= 0x40) {  in read_clk()
68 		if (device->chipset == 0xaf) {  in read_clk()
70 			return nvkm_rd32(device, 0x00471c) * 1000;  in read_clk()
76 	sctl = nvkm_rd32(device, 0x4120 + (idx * 4));  in read_clk()
77 	if (!ignore_en && !(sctl & 0x00000100))  in read_clk()
78 		return 0;  in read_clk()
81 	if (sctl & 0x00000400)  in read_clk()
85 	switch (sctl & 0x00003000) {  in read_clk()
86 	case 0x00000000:  in read_clk()
87 		if (!(sctl & 0x00000200))  in read_clk()
89 		return 0;  in read_clk()
90 	case 0x00002000:  in read_clk()
91 		if (sctl & 0x00000040)  in read_clk()
94 	case 0x00003000:  in read_clk()
96 		if (!(sctl & 0x00000001))  in read_clk()
97 			return 0;  in read_clk()
100 		sdiv = ((sctl & 0x003f0000) >> 16) + 2;  in read_clk()
103 		return 0;  in read_clk()
111 	u32 ctrl = nvkm_rd32(device, pll + 0);  in read_pll()
112 	u32 sclk = 0, P = 1, N = 1, M = 1;  in read_pll()
115 	if (!(ctrl & 0x00000008)) {  in read_pll()
116 		if (ctrl & 0x00000001) {  in read_pll()
118 			M = (coef & 0x000000ff) >> 0;  in read_pll()
119 			N = (coef & 0x0000ff00) >> 8;  in read_pll()
120 			P = (coef & 0x003f0000) >> 16;  in read_pll()
125 			if ((pll & 0x00ff00) == 0x00e800)  in read_pll()
128 			sclk = read_clk(clk, 0x00 + idx, false);  in read_pll()
131 		sclk = read_clk(clk, 0x10 + idx, false);  in read_pll()
137 		return 0;  in read_pll()
155 		return read_pll(clk, 0x00, 0x4200);  in gt215_clk_read()
157 		return read_pll(clk, 0x01, 0x4220);  in gt215_clk_read()
159 		return read_pll(clk, 0x02, 0x4000);  in gt215_clk_read()
161 		return read_clk(clk, 0x20, false);  in gt215_clk_read()
163 		return read_clk(clk, 0x21, false);  in gt215_clk_read()
165 		return read_clk(clk, 0x25, false);  in gt215_clk_read()
167 		hsrc = (nvkm_rd32(device, 0xc040) & 0x30000000) >> 28;  in gt215_clk_read()
169 		case 0:  in gt215_clk_read()
170 			return read_clk(clk, 0x1d, false);  in gt215_clk_read()
183 	return 0;  in gt215_clk_read()
194 	info->clk = 0;  in gt215_clk_info()
198 		info->clk = 0x00000100;  in gt215_clk_info()
201 		info->clk = 0x00002100;  in gt215_clk_info()
204 		info->clk = 0x00002140;  in gt215_clk_info()
214 		if (diff < 0) {  in gt215_clk_info()
224 			info->clk = (((sdiv - 2) << 16) | 0x00003100);  in gt215_clk_info()
244 	info->pll = 0;  in gt215_pll_info()
259 	ret = gt215_clk_info(&clk->base, idx - 0x10, limits.refclk, info);  in gt215_pll_info()
264 	if (ret >= 0) {  in gt215_pll_info()
279 	if (ret >= 0)  in calc_clk()
280 		return 0;  in calc_clk()
287 	int ret = 0;  in calc_host()
292 		info->clk = 0;  in calc_host()
294 		return 0;  in calc_host()
299 	ret = gt215_clk_info(&clk->base, 0x1d, kHz, info);  in calc_host()
300 	if (ret >= 0)  in calc_host()
301 		return 0;  in calc_host()
313 	nvkm_mask(device, 0x020060, 0x00070000, 0x00000000);  in gt215_clk_pre()
314 	nvkm_mask(device, 0x002504, 0x00000001, 0x00000001);  in gt215_clk_pre()
317 		if (!nvkm_rd32(device, 0x000100))  in gt215_clk_pre()
319 	) < 0)  in gt215_clk_pre()
326 		if (nvkm_rd32(device, 0x002504) & 0x00000010)  in gt215_clk_pre()
328 	) < 0)  in gt215_clk_pre()
332 		u32 tmp = nvkm_rd32(device, 0x00251c) & 0x0000003f;  in gt215_clk_pre()
333 		if (tmp == 0x0000003f)  in gt215_clk_pre()
335 	) < 0)  in gt215_clk_pre()
338 	return 0;  in gt215_clk_pre()
350 	nvkm_mask(device, 0x002504, 0x00000001, 0x00000000);  in gt215_clk_post()
351 	nvkm_mask(device, 0x020060, 0x00070000, 0x00040000);  in gt215_clk_post()
358 	nvkm_mask(device, src, 0x00000100, 0x00000000);  in disable_clk_src()
359 	nvkm_mask(device, src, 0x00000001, 0x00000000);  in disable_clk_src()
367 	const u32 src0 = 0x004120 + (idx * 4);  in prog_pll()
368 	const u32 src1 = 0x004160 + (idx * 4);  in prog_pll()
369 	const u32 ctrl = pll + 0;  in prog_pll()
375 		bypass = nvkm_rd32(device, ctrl)  & 0x00000008;  in prog_pll()
377 			nvkm_mask(device, src1, 0x00000101, 0x00000101);  in prog_pll()
378 			nvkm_mask(device, ctrl, 0x00000008, 0x00000008);  in prog_pll()
382 		nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk);  in prog_pll()
384 		nvkm_mask(device, ctrl, 0x00000015, 0x00000015);  in prog_pll()
385 		nvkm_mask(device, ctrl, 0x00000010, 0x00000000);  in prog_pll()
387 			if (nvkm_rd32(device, ctrl) & 0x00020000)  in prog_pll()
389 		) < 0) {  in prog_pll()
390 			nvkm_mask(device, ctrl, 0x00000010, 0x00000010);  in prog_pll()
391 			nvkm_mask(device, src0, 0x00000101, 0x00000000);  in prog_pll()
394 		nvkm_mask(device, ctrl, 0x00000010, 0x00000010);  in prog_pll()
395 		nvkm_mask(device, ctrl, 0x00000008, 0x00000000);  in prog_pll()
398 		nvkm_mask(device, src1, 0x003f3141, 0x00000101 | info->clk);  in prog_pll()
399 		nvkm_mask(device, ctrl, 0x00000018, 0x00000018);  in prog_pll()
401 		nvkm_mask(device, ctrl, 0x00000001, 0x00000000);  in prog_pll()
411 	nvkm_mask(device, 0x004120 + (idx * 4), 0x003f3141, 0x00000101 | info->clk);  in prog_clk()
419 	u32 hsrc = (nvkm_rd32(device, 0xc040));  in prog_host()
423 		if ((hsrc & 0x30000000) == 0) {  in prog_host()
424 			nvkm_wr32(device, 0xc040, hsrc | 0x20000000);  in prog_host()
425 			disable_clk_src(clk, 0x4194);  in prog_host()
429 		prog_clk(clk, 0x1d, nv_clk_src_host);  in prog_host()
430 		if ((hsrc & 0x30000000) >= 0x20000000) {  in prog_host()
431 			nvkm_wr32(device, 0xc040, hsrc & ~0x30000000);  in prog_host()
439 	nvkm_wr32(device, 0xc044, 0x3e);  in prog_host()
447 	u32 fb_delay = nvkm_rd32(device, 0x10002c);  in prog_core()
450 		nvkm_wr32(device, 0x10002c, info->fb_delay);  in prog_core()
452 	prog_pll(clk, 0x00, 0x004200, dom);  in prog_core()
455 		nvkm_wr32(device, 0x10002c, info->fb_delay);  in prog_core()
465 	if ((ret = calc_clk(clk, cstate, 0x10, 0x4200, nv_clk_src_core)) ||  in gt215_clk_calc()
466 	    (ret = calc_clk(clk, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||  in gt215_clk_calc()
467 	    (ret = calc_clk(clk, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||  in gt215_clk_calc()
468 	    (ret = calc_clk(clk, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||  in gt215_clk_calc()
475 		ret = gt215_clk_info(&clk->base, 0x10,  in gt215_clk_calc()
478 		if (ret < 0)  in gt215_clk_calc()
482 	return 0;  in gt215_clk_calc()
490 	int ret = 0;  in gt215_clk_prog()
502 	prog_pll(clk, 0x01, 0x004220, nv_clk_src_shader);  in gt215_clk_prog()
503 	prog_clk(clk, 0x20, nv_clk_src_disp);  in gt215_clk_prog()
504 	prog_clk(clk, 0x21, nv_clk_src_vdec);  in gt215_clk_prog()
527 		{ nv_clk_src_crystal  , 0xff },
528 		{ nv_clk_src_core     , 0x00, 0, "core", 1000 },
529 		{ nv_clk_src_shader   , 0x01, 0, "shader", 1000 },
530 		{ nv_clk_src_mem      , 0x02, 0, "memory", 1000 },
531 		{ nv_clk_src_vdec     , 0x03 },
532 		{ nv_clk_src_disp     , 0x04 },
533 		{ nv_clk_src_host     , 0x05 },
534 		{ nv_clk_src_core_intm, 0x06 },