Lines Matching +full:0 +full:x101000
42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
44 '0' + (init->nested - 1) : ' ', ##args); \
45 } while(0)
49 } while(0)
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
74 init->execute ^= 0x02; in init_exec_inv()
80 if (exec) init->execute |= 0x04; in init_exec_force()
81 else init->execute &= 0xfb; in init_exec_force()
92 if (init->or >= 0) in init_or()
96 return 0; in init_or()
107 return 0; in init_link()
114 if (init->head >= 0) in init_head()
118 return 0; in init_head()
140 return 0xff; in init_conn()
154 reg &= ~0x00000003; in init_nvreg()
160 if (reg & 0x80000000) { in init_nvreg()
161 reg += init_head(init) * 0x800; in init_nvreg()
162 reg &= ~0x80000000; in init_nvreg()
165 if (reg & 0x40000000) { in init_nvreg()
166 reg += init_or(init) * 0x800; in init_nvreg()
167 reg &= ~0x40000000; in init_nvreg()
168 if (reg & 0x20000000) { in init_nvreg()
169 reg += init_link(init) * 0x80; in init_nvreg()
170 reg &= ~0x20000000; in init_nvreg()
175 if (reg & ~0x00fffffc) in init_nvreg()
176 warn("unknown bits in register 0x%08x\n", reg); in init_nvreg()
186 if (reg != ~0 && init_exec(init)) in init_rd32()
188 return 0x00000000; in init_rd32()
196 if (reg != ~0 && init_exec(init)) in init_wr32()
205 if (reg != ~0 && init_exec(init)) { in init_mask()
210 return 0x00000000; in init_mask()
218 return 0x00; in init_rdport()
233 int head = init->head < 0 ? 0 : init->head; in init_rdvgai()
236 return 0x00; in init_rdvgai()
244 /* force head 0 for updates to cr44, it only exists on first head */ in init_wrvgai()
246 if (port == 0x03d4 && index == 0x44) in init_wrvgai()
247 init->head = 0; in init_wrvgai()
251 int head = init->head < 0 ? 0 : init->head; in init_wrvgai()
257 if (port == 0x03d4 && index == 0x44 && value == 3) in init_wrvgai()
268 if (index == 0xff) { in init_i2c()
273 if (index == 0x80) { in init_i2c()
276 if (index == 0x81) { in init_i2c()
322 if (ret == 0) in init_rdauxr()
327 return 0x00; in init_rdauxr()
350 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); in init_prog_pll()
368 if (bmp_version(bios) >= 0x0510) { in init_table()
373 return 0x0000; in init_table()
388 return 0x0000; in init_table_()
392 return 0x0000; in init_table_()
396 return 0x0000; in init_table_()
399 #define init_script_table(b) init_table_((b), 0x00, "script table")
400 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
401 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
402 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
403 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
404 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag condition table")
405 #define init_function_table(b) init_table_((b), 0x0c, "function table")
406 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
414 if (bmp_ver && bmp_ver < 0x0510) { in init_script()
415 if (index > 1 || bmp_ver < 0x0100) in init_script()
416 return 0x0000; in init_script()
418 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); in init_script()
426 return 0x0000; in init_script()
435 return 0x0000; in init_unknown_script()
455 if (!init->ramcfg || init->subdev->device->bios->version.major < 0x70) in init_ram_restrict()
456 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); in init_ram_restrict()
457 return (init->ramcfg & 0x7fffffff); in init_ram_restrict()
471 return 0x00; in init_xlat_()
484 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); in init_condition_met()
487 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", in init_condition_met()
500 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0); in init_io_condition_met()
504 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", in init_io_condition_met()
517 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0); in init_io_flag_condition_met()
533 if (shift < 0x80) in init_shift()
535 return data << (0x100 - shift); in init_shift()
541 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. in init_tmds_reg()
542 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by in init_tmds_reg()
543 * CR58 for CR57 = 0 to index a table of offsets to the basic in init_tmds_reg()
544 * 0x6808b0 address. in init_tmds_reg()
545 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by in init_tmds_reg()
546 * CR58 for CR57 = 0 to index a table of offsets to the basic in init_tmds_reg()
547 * 0x6808b0 address, and then flip the offset by 8. in init_tmds_reg()
550 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; in init_tmds_reg()
552 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; in init_tmds_reg()
554 if (tmds >= 0x80) { in init_tmds_reg()
557 if (tmds == 0x81) in init_tmds_reg()
559 return 0x6808b0 + dacoffset; in init_tmds_reg()
568 error("tmds selector 0x%02x unknown\n", tmds); in init_tmds_reg()
571 return 0; in init_tmds_reg()
590 case 0xaa: in init_reserved()
598 trace("RESERVED 0x%02x\t", opcode); in init_reserved()
600 cont(" 0x%02x", nvbios_rd08(bios, init->offset + i)); in init_reserved()
606 * INIT_DONE - opcode 0x71
613 init->offset = 0x0000; in init_done()
617 * INIT_IO_RESTRICT_PROG - opcode 0x32
632 trace("IO_RESTRICT_PROG\tR[0x%06x] = " in init_io_restrict_prog()
633 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", in init_io_restrict_prog()
638 for (i = 0; i < count; i++) { in init_io_restrict_prog()
654 * INIT_REPEAT - opcode 0x33
680 * INIT_IO_RESTRICT_PLL - opcode 0x34
696 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " in init_io_restrict_pll()
697 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", in init_io_restrict_pll()
702 for (i = 0; i < count; i++) { in init_io_restrict_pll()
707 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) in init_io_restrict_pll()
720 * INIT_END_REPEAT - opcode 0x36
731 init->offset = 0; in init_end_repeat()
736 * INIT_COPY - opcode 0x37
751 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " in init_copy()
752 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", in init_copy()
753 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", in init_copy()
754 (shift & 0x80) ? (0x100 - shift) : shift, smask); in init_copy()
763 * INIT_NOT - opcode 0x38
775 * INIT_IO_FLAG_CONDITION - opcode 0x39
792 * INIT_GENERIC_CONDITION - opcode 0x3a
805 trace("GENERIC_CONDITION\t0x%02x 0x%02x\n", cond, size); in init_generic_condition()
809 case 0: /* CONDITION_ID_INT_DP. */ in init_generic_condition()
817 (init->outp->or << 0) | in init_generic_condition()
830 if (!(init_rdauxr(init, 0x0d) & 1)) in init_generic_condition()
837 warn("INIT_GENERIC_CONDITION: unknown 0x%02x\n", cond); in init_generic_condition()
844 * INIT_IO_MASK_OR - opcode 0x3b
855 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); in init_io_mask_or()
858 data = init_rdvgai(init, 0x03d4, index); in init_io_mask_or()
859 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); in init_io_mask_or()
863 * INIT_IO_OR - opcode 0x3c
874 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); in init_io_or()
877 data = init_rdvgai(init, 0x03d4, index); in init_io_or()
878 init_wrvgai(init, 0x03d4, index, data | (1 << or)); in init_io_or()
882 * INIT_ANDN_REG - opcode 0x47
892 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); in init_andn_reg()
895 init_mask(init, reg, mask, 0); in init_andn_reg()
899 * INIT_OR_REG - opcode 0x48
909 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); in init_or_reg()
912 init_mask(init, reg, 0, mask); in init_or_reg()
916 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
929 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); in init_idx_addr_latched()
930 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); in init_idx_addr_latched()
934 u8 iaddr = nvbios_rd08(bios, init->offset + 0); in init_idx_addr_latched()
937 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); in init_idx_addr_latched()
946 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
962 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", in init_io_restrict_pll2()
967 for (i = 0; i < count; i++) { in init_io_restrict_pll2()
981 * INIT_PLL2 - opcode 0x4b
991 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); in init_pll2()
998 * INIT_I2C_BYTE - opcode 0x4c
1009 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); in init_i2c_byte()
1013 u8 reg = nvbios_rd08(bios, init->offset + 0); in init_i2c_byte()
1018 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); in init_i2c_byte()
1022 if (val < 0) in init_i2c_byte()
1029 * INIT_ZM_I2C_BYTE - opcode 0x4d
1040 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); in init_zm_i2c_byte()
1044 u8 reg = nvbios_rd08(bios, init->offset + 0); in init_zm_i2c_byte()
1047 trace("\t[0x%02x] = 0x%02x\n", reg, data); in init_zm_i2c_byte()
1055 * INIT_ZM_I2C - opcode 0x4e
1067 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); in init_zm_i2c()
1070 for (i = 0; i < count; i++) { in init_zm_i2c()
1079 .addr = addr, .flags = 0, .len = count, .buf = data, in init_zm_i2c()
1089 * INIT_TMDS - opcode 0x4f
1102 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", in init_tmds()
1106 if (reg == 0) in init_tmds()
1109 init_wr32(init, reg + 0, addr | 0x00010000); in init_tmds()
1111 init_wr32(init, reg + 0, addr); in init_tmds()
1115 * INIT_ZM_TMDS_GROUP - opcode 0x50
1126 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); in init_zm_tmds_group()
1130 u8 addr = nvbios_rd08(bios, init->offset + 0); in init_zm_tmds_group()
1133 trace("\t[0x%02x] = 0x%02x\n", addr, data); in init_zm_tmds_group()
1137 init_wr32(init, reg + 0, addr); in init_zm_tmds_group()
1142 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1158 save0 = init_rdvgai(init, 0x03d4, addr0); in init_cr_idx_adr_latch()
1162 trace("\t\t[0x%02x] = 0x%02x\n", base, data); in init_cr_idx_adr_latch()
1165 init_wrvgai(init, 0x03d4, addr0, base++); in init_cr_idx_adr_latch()
1166 init_wrvgai(init, 0x03d4, addr1, data); in init_cr_idx_adr_latch()
1168 init_wrvgai(init, 0x03d4, addr0, save0); in init_cr_idx_adr_latch()
1172 * INIT_CR - opcode 0x52
1184 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); in init_cr()
1187 val = init_rdvgai(init, 0x03d4, addr) & mask; in init_cr()
1188 init_wrvgai(init, 0x03d4, addr, val | data); in init_cr()
1192 * INIT_ZM_CR - opcode 0x53
1202 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); in init_zm_cr()
1205 init_wrvgai(init, 0x03d4, addr, data); in init_zm_cr()
1209 * INIT_ZM_CR_GROUP - opcode 0x54
1222 u8 addr = nvbios_rd08(bios, init->offset + 0); in init_zm_cr_group()
1225 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); in init_zm_cr_group()
1228 init_wrvgai(init, 0x03d4, addr, data); in init_zm_cr_group()
1233 * INIT_CONDITION_TIME - opcode 0x56
1244 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); in init_condition_time()
1260 * INIT_LTIME - opcode 0x57
1277 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1293 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); in init_zm_reg_sequence()
1302 * INIT_PLL_INDIRECT - opcode 0x59
1313 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", in init_pll_indirect()
1321 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1332 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", in init_zm_reg_indirect()
1340 * INIT_SUB_DIRECT - opcode 0x5b
1366 * INIT_JUMP - opcode 0x5c
1384 * INIT_I2C_IF - opcode 0x5e
1398 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", in init_i2c_if()
1411 * INIT_COPY_NV_REG - opcode 0x5f
1426 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " in init_copy_nv_reg()
1427 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", in init_copy_nv_reg()
1428 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", in init_copy_nv_reg()
1429 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); in init_copy_nv_reg()
1437 * INIT_ZM_INDEX_IO - opcode 0x62
1448 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); in init_zm_index_io()
1455 * INIT_COMPUTE_MEM - opcode 0x63
1473 * INIT_RESET - opcode 0x65
1485 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); in init_reset()
1489 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); in init_reset()
1493 init_wr32(init, 0x00184c, savepci19); in init_reset()
1494 init_mask(init, 0x001850, 0x00000001, 0x00000000); in init_reset()
1500 * INIT_CONFIGURE_MEM - opcode 0x66
1508 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; in init_configure_mem_clk()
1530 if (nvbios_rd08(bios, mdata) & 0x01) in init_configure_mem()
1534 data = init_rdvgai(init, 0x03c4, 0x01); in init_configure_mem()
1535 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); in init_configure_mem()
1537 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) { in init_configure_mem()
1539 case 0x10021c: /* CKE_NORMAL */ in init_configure_mem()
1540 case 0x1002d0: /* CMD_REFRESH */ in init_configure_mem()
1541 case 0x1002d4: /* CMD_PRECHARGE */ in init_configure_mem()
1542 data = 0x00000001; in init_configure_mem()
1547 if (data == 0xffffffff) in init_configure_mem()
1559 * INIT_CONFIGURE_CLK - opcode 0x67
1581 init_prog_pll(init, 0x680500, clock); in init_configure_clk()
1585 if (nvbios_rd08(bios, mdata) & 0x01) in init_configure_clk()
1587 init_prog_pll(init, 0x680504, clock); in init_configure_clk()
1593 * INIT_CONFIGURE_PREINIT - opcode 0x68
1611 strap = init_rd32(init, 0x101000); in init_configure_preinit()
1612 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); in init_configure_preinit()
1613 init_wrvgai(init, 0x03d4, 0x3c, strap); in init_configure_preinit()
1619 * INIT_IO - opcode 0x69
1631 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); in init_io()
1639 port == 0x03c3 && data == 0x01) { in init_io()
1640 init_mask(init, 0x614100, 0xf0800000, 0x00800000); in init_io()
1641 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); in init_io()
1642 init_mask(init, 0x614900, 0xf0800000, 0x00800000); in init_io()
1643 init_mask(init, 0x000200, 0x40000000, 0x00000000); in init_io()
1645 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); in init_io()
1646 init_mask(init, 0x000200, 0x40000000, 0x40000000); in init_io()
1647 init_wr32(init, 0x614100, 0x00800018); in init_io()
1648 init_wr32(init, 0x614900, 0x00800018); in init_io()
1650 init_wr32(init, 0x614100, 0x10000018); in init_io()
1651 init_wr32(init, 0x614900, 0x10000018); in init_io()
1659 * INIT_SUB - opcode 0x6b
1686 * INIT_RAM_CONDITION - opcode 0x6d
1697 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); in init_ram_condition()
1700 if ((init_rd32(init, 0x100000) & mask) != value) in init_ram_condition()
1705 * INIT_NV_REG - opcode 0x6e
1716 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); in init_nv_reg()
1723 * INIT_MACRO - opcode 0x6f
1737 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0); in init_macro()
1739 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); in init_macro()
1747 * INIT_RESUME - opcode 0x72
1759 * INIT_STRAP_CONDITION - opcode 0x73
1769 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); in init_strap_condition()
1772 if ((init_rd32(init, 0x101000) & mask) != value) in init_strap_condition()
1777 * INIT_TIME - opcode 0x74
1798 * INIT_CONDITION - opcode 0x75
1815 * INIT_IO_CONDITION - opcode 0x76
1832 * INIT_ZM_REG16 - opcode 0x77
1842 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); in init_zm_reg16()
1849 * INIT_INDEX_IO - opcode 0x78
1862 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", in init_index_io()
1871 * INIT_PLL - opcode 0x79
1881 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); in init_pll()
1888 * INIT_ZM_REG - opcode 0x7a
1898 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); in init_zm_reg()
1901 if (addr == 0x000200) in init_zm_reg()
1902 data |= 0x00000001; in init_zm_reg()
1908 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1923 for (cconf = 0; cconf < count; cconf++) { in init_ram_restrict_pll()
1938 * INIT_RESET_BEGUN - opcode 0x8c
1949 * INIT_RESET_END - opcode 0x8d
1960 * INIT_GPIO - opcode 0x8e
1976 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1991 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); in init_ram_restrict_zm_reg_group()
1994 for (i = 0; i < num; i++) { in init_ram_restrict_zm_reg_group()
1995 trace("\tR[0x%06x] = {\n", addr); in init_ram_restrict_zm_reg_group()
1996 for (j = 0; j < count; j++) { in init_ram_restrict_zm_reg_group()
2014 * INIT_COPY_ZM_REG - opcode 0x90
2024 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); in init_copy_zm_reg()
2031 * INIT_ZM_REG_GROUP - opcode 0x91
2041 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); in init_zm_reg_group()
2053 * INIT_XLAT - opcode 0x96
2069 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " in init_xlat()
2070 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", in init_xlat()
2071 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", in init_xlat()
2072 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); in init_xlat()
2081 * INIT_ZM_MASK_ADD - opcode 0x97
2093 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); in init_zm_mask_add()
2102 * INIT_AUXCH - opcode 0x98
2112 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); in init_auxch()
2116 u8 mask = nvbios_rd08(bios, init->offset + 0); in init_auxch()
2118 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); in init_auxch()
2126 * INIT_AUXCH - opcode 0x99
2136 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); in init_zm_auxch()
2140 u8 data = nvbios_rd08(bios, init->offset + 0); in init_zm_auxch()
2141 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); in init_zm_auxch()
2148 * INIT_I2C_LONG_IF - opcode 0x9a
2164 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", in init_i2c_long_if()
2173 { .addr = addr, .flags = 0, .len = 2, .buf = i }, in init_i2c_long_if()
2179 if (ret == 2 && ((o[0] & mask) == data)) in init_i2c_long_if()
2187 * INIT_GPIO_NE - opcode 0xa9
2197 u8 idx = 0, ver, len; in init_gpio_ne()
2204 cont("0x%02x ", nvbios_rd08(bios, i)); in init_gpio_ne()
2207 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { in init_gpio_ne()
2214 trace("\tFUNC[0x%02x]", func.func); in init_gpio_ne()
2230 [0x32] = { init_io_restrict_prog },
2231 [0x33] = { init_repeat },
2232 [0x34] = { init_io_restrict_pll },
2233 [0x36] = { init_end_repeat },
2234 [0x37] = { init_copy },
2235 [0x38] = { init_not },
2236 [0x39] = { init_io_flag_condition },
2237 [0x3a] = { init_generic_condition },
2238 [0x3b] = { init_io_mask_or },
2239 [0x3c] = { init_io_or },
2240 [0x47] = { init_andn_reg },
2241 [0x48] = { init_or_reg },
2242 [0x49] = { init_idx_addr_latched },
2243 [0x4a] = { init_io_restrict_pll2 },
2244 [0x4b] = { init_pll2 },
2245 [0x4c] = { init_i2c_byte },
2246 [0x4d] = { init_zm_i2c_byte },
2247 [0x4e] = { init_zm_i2c },
2248 [0x4f] = { init_tmds },
2249 [0x50] = { init_zm_tmds_group },
2250 [0x51] = { init_cr_idx_adr_latch },
2251 [0x52] = { init_cr },
2252 [0x53] = { init_zm_cr },
2253 [0x54] = { init_zm_cr_group },
2254 [0x56] = { init_condition_time },
2255 [0x57] = { init_ltime },
2256 [0x58] = { init_zm_reg_sequence },
2257 [0x59] = { init_pll_indirect },
2258 [0x5a] = { init_zm_reg_indirect },
2259 [0x5b] = { init_sub_direct },
2260 [0x5c] = { init_jump },
2261 [0x5e] = { init_i2c_if },
2262 [0x5f] = { init_copy_nv_reg },
2263 [0x62] = { init_zm_index_io },
2264 [0x63] = { init_compute_mem },
2265 [0x65] = { init_reset },
2266 [0x66] = { init_configure_mem },
2267 [0x67] = { init_configure_clk },
2268 [0x68] = { init_configure_preinit },
2269 [0x69] = { init_io },
2270 [0x6b] = { init_sub },
2271 [0x6d] = { init_ram_condition },
2272 [0x6e] = { init_nv_reg },
2273 [0x6f] = { init_macro },
2274 [0x71] = { init_done },
2275 [0x72] = { init_resume },
2276 [0x73] = { init_strap_condition },
2277 [0x74] = { init_time },
2278 [0x75] = { init_condition },
2279 [0x76] = { init_io_condition },
2280 [0x77] = { init_zm_reg16 },
2281 [0x78] = { init_index_io },
2282 [0x79] = { init_pll },
2283 [0x7a] = { init_zm_reg },
2284 [0x87] = { init_ram_restrict_pll },
2285 [0x8c] = { init_reset_begun },
2286 [0x8d] = { init_reset_end },
2287 [0x8e] = { init_gpio },
2288 [0x8f] = { init_ram_restrict_zm_reg_group },
2289 [0x90] = { init_copy_zm_reg },
2290 [0x91] = { init_zm_reg_group },
2291 [0x92] = { init_reserved },
2292 [0x96] = { init_xlat },
2293 [0x97] = { init_zm_mask_add },
2294 [0x98] = { init_auxch },
2295 [0x99] = { init_zm_auxch },
2296 [0x9a] = { init_i2c_long_if },
2297 [0xa9] = { init_gpio_ne },
2298 [0xaa] = { init_reserved },
2311 error("unknown opcode 0x%02x\n", opcode); in nvbios_exec()
2318 return 0; in nvbios_exec()
2325 int ret = 0; in nvbios_post()
2333 init.execute = execute ? 1 : 0; in nvbios_post()
2342 init.execute = execute ? 1 : 0; in nvbios_post()