Lines Matching +full:mem +full:- +full:base
32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush() argument
34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush()
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm() argument
49 return nv50_bar(base)->bar1_vmm; in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait() argument
55 nvkm_bar_flush(base); in nv50_bar_bar1_wait()
61 nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000); in nv50_bar_bar1_fini()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init() argument
67 struct nvkm_device *device = base->subdev.device; in nv50_bar_bar1_init()
68 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_bar1_init()
69 nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4); in nv50_bar_bar1_init()
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) in nv50_bar_bar2_vmm() argument
75 return nv50_bar(base)->bar2_vmm; in nv50_bar_bar2_vmm()
81 nvkm_wr32(bar->subdev.device, 0x00170c, 0x00000000); in nv50_bar_bar2_fini()
85 nv50_bar_bar2_init(struct nvkm_bar *base) in nv50_bar_bar2_init() argument
87 struct nvkm_device *device = base->subdev.device; in nv50_bar_bar2_init()
88 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_bar2_init()
89 nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12); in nv50_bar_bar2_init()
90 nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12); in nv50_bar_bar2_init()
91 nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4); in nv50_bar_bar2_init()
95 nv50_bar_init(struct nvkm_bar *base) in nv50_bar_init() argument
97 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_init()
98 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_init()
106 nv50_bar_oneinit(struct nvkm_bar *base) in nv50_bar_oneinit() argument
108 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_oneinit()
109 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_oneinit()
115 ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem); in nv50_bar_oneinit()
119 ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem, in nv50_bar_oneinit()
120 &bar->pad); in nv50_bar_oneinit()
124 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd); in nv50_bar_oneinit()
130 size = device->func->resource_size(device, 3); in nv50_bar_oneinit()
132 return -ENOMEM; in nv50_bar_oneinit()
135 ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0, in nv50_bar_oneinit()
136 &bar2_lock, "bar2", &bar->bar2_vmm); in nv50_bar_oneinit()
140 atomic_inc(&bar->bar2_vmm->engref[NVKM_SUBDEV_BAR]); in nv50_bar_oneinit()
141 bar->bar2_vmm->debug = bar->base.subdev.debug; in nv50_bar_oneinit()
143 ret = nvkm_vmm_boot(bar->bar2_vmm); in nv50_bar_oneinit()
147 ret = nvkm_vmm_join(bar->bar2_vmm, bar->mem->memory); in nv50_bar_oneinit()
151 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2); in nv50_bar_oneinit()
155 nvkm_kmap(bar->bar2); in nv50_bar_oneinit()
156 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); in nv50_bar_oneinit()
157 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
158 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
159 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
161 nvkm_wo32(bar->bar2, 0x10, 0x00000000); in nv50_bar_oneinit()
162 nvkm_wo32(bar->bar2, 0x14, 0x00000000); in nv50_bar_oneinit()
163 nvkm_done(bar->bar2); in nv50_bar_oneinit()
165 bar->base.subdev.oneinit = true; in nv50_bar_oneinit()
170 size = device->func->resource_size(device, 1); in nv50_bar_oneinit()
172 return -ENOMEM; in nv50_bar_oneinit()
175 ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0, in nv50_bar_oneinit()
176 &bar1_lock, "bar1", &bar->bar1_vmm); in nv50_bar_oneinit()
180 atomic_inc(&bar->bar1_vmm->engref[NVKM_SUBDEV_BAR]); in nv50_bar_oneinit()
181 bar->bar1_vmm->debug = bar->base.subdev.debug; in nv50_bar_oneinit()
183 ret = nvkm_vmm_join(bar->bar1_vmm, bar->mem->memory); in nv50_bar_oneinit()
187 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1); in nv50_bar_oneinit()
191 nvkm_kmap(bar->bar1); in nv50_bar_oneinit()
192 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); in nv50_bar_oneinit()
193 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
194 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
195 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
197 nvkm_wo32(bar->bar1, 0x10, 0x00000000); in nv50_bar_oneinit()
198 nvkm_wo32(bar->bar1, 0x14, 0x00000000); in nv50_bar_oneinit()
199 nvkm_done(bar->bar1); in nv50_bar_oneinit()
204 nv50_bar_dtor(struct nvkm_bar *base) in nv50_bar_dtor() argument
206 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_dtor()
207 if (bar->mem) { in nv50_bar_dtor()
208 nvkm_gpuobj_del(&bar->bar1); in nv50_bar_dtor()
209 nvkm_vmm_part(bar->bar1_vmm, bar->mem->memory); in nv50_bar_dtor()
210 nvkm_vmm_unref(&bar->bar1_vmm); in nv50_bar_dtor()
211 nvkm_gpuobj_del(&bar->bar2); in nv50_bar_dtor()
212 nvkm_vmm_part(bar->bar2_vmm, bar->mem->memory); in nv50_bar_dtor()
213 nvkm_vmm_unref(&bar->bar2_vmm); in nv50_bar_dtor()
214 nvkm_gpuobj_del(&bar->pgd); in nv50_bar_dtor()
215 nvkm_gpuobj_del(&bar->pad); in nv50_bar_dtor()
216 nvkm_gpuobj_del(&bar->mem); in nv50_bar_dtor()
227 return -ENOMEM; in nv50_bar_new_()
228 nvkm_bar_ctor(func, device, type, inst, &bar->base); in nv50_bar_new_()
229 bar->pgd_addr = pgd_addr; in nv50_bar_new_()
230 *pbar = &bar->base; in nv50_bar_new_()