31 	u32 sctl = nvkm_falcon_rd32(falcon, 0x240);  in gm200_flcn_tracepc()
32 	u32 tidx = nvkm_falcon_rd32(falcon, 0x148);  in gm200_flcn_tracepc()
33 	int nr = (tidx & 0x00ff0000) >> 16, sp, ip;  in gm200_flcn_tracepc()
36 	for (sp = 0; sp < nr; sp++) {  in gm200_flcn_tracepc()
37 		nvkm_falcon_wr32(falcon, 0x148, sp);  in gm200_flcn_tracepc()
38 		ip = nvkm_falcon_rd32(falcon, 0x14c);  in gm200_flcn_tracepc()
47 		*(u32 *)img = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));  in gm200_flcn_pio_dmem_rd()
54 		u32 data = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));  in gm200_flcn_pio_dmem_rd()
57 			*(u8 *)img++ = data & 0xff;  in gm200_flcn_pio_dmem_rd()
66 	nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), BIT(25) | dmem_base);  in gm200_flcn_pio_dmem_rd_init()
73 		nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), *(u32 *)img);  in gm200_flcn_pio_dmem_wr()
84 	nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), BIT(24) | dmem_base);  in gm200_flcn_pio_dmem_wr_init()
90 	.max = 0x100,
100 	nvkm_falcon_wr32(falcon, 0x180 + (port * 0x10), (sec ? BIT(28) : 0) | BIT(24) | imem_base);  in gm200_flcn_pio_imem_wr_init()
106 	nvkm_falcon_wr32(falcon, 0x188 + (port * 0x10), tag++);  in gm200_flcn_pio_imem_wr()
108 		nvkm_falcon_wr32(falcon, 0x184 + (port * 0x10), *(u32 *)img);  in gm200_flcn_pio_imem_wr()
116 	.min = 0x100,
117 	.max = 0x100,
125 	if (intr && !(nvkm_falcon_rd32(falcon, 0x008) & 0x00000008))  in gm200_flcn_bind_stat()
128 	return (nvkm_falcon_rd32(falcon, 0x0dc) & 0x00007000) >> 12;  in gm200_flcn_bind_stat()
134 	nvkm_falcon_mask(falcon, 0x604, 0x00000007, 0x00000000); /* DMAIDX_VIRT */  in gm200_flcn_bind_inst()
135 	nvkm_falcon_wr32(falcon, 0x054, (1 << 30) | (target << 28) | (addr >> 12));  in gm200_flcn_bind_inst()
136 	nvkm_falcon_mask(falcon, 0x090, 0x00010000, 0x00010000);  in gm200_flcn_bind_inst()
137 	nvkm_falcon_mask(falcon, 0x0a4, 0x00000008, 0x00000008);  in gm200_flcn_bind_inst()
143 	nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000);  in gm200_flcn_reset_wait_mem_scrubbing()
146 		if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006))  in gm200_flcn_reset_wait_mem_scrubbing()
148 	) < 0)  in gm200_flcn_reset_wait_mem_scrubbing()
151 	return 0;  in gm200_flcn_reset_wait_mem_scrubbing()
179 	nvkm_falcon_wr32(falcon, 0x084, nvkm_rd32(device, 0x000000));  in gm200_flcn_enable()
180 	return 0;  in gm200_flcn_enable()
195 	nvkm_falcon_mask(falcon, 0x048, 0x00000003, 0x00000000);  in gm200_flcn_disable()
196 	nvkm_falcon_wr32(falcon, 0x014, 0xffffffff);  in gm200_flcn_disable()
214 	return 0;  in gm200_flcn_disable()
222 	int ret = 0;  in gm200_flcn_fw_boot()
224 	nvkm_falcon_wr32(falcon, 0x040, pmbox0 ? *pmbox0 : 0xcafebeef);  in gm200_flcn_fw_boot()
226 		nvkm_falcon_wr32(falcon, 0x044, *pmbox1);  in gm200_flcn_fw_boot()
228 	nvkm_falcon_wr32(falcon, 0x104, fw->boot_addr);  in gm200_flcn_fw_boot()
229 	nvkm_falcon_wr32(falcon, 0x100, 0x00000002);  in gm200_flcn_fw_boot()
232 		if (nvkm_falcon_rd32(falcon, 0x100) & 0x00000010)  in gm200_flcn_fw_boot()
234 	) < 0)  in gm200_flcn_fw_boot()
237 	mbox0 = nvkm_falcon_rd32(falcon, 0x040);  in gm200_flcn_fw_boot()
238 	mbox1 = nvkm_falcon_rd32(falcon, 0x044);  in gm200_flcn_fw_boot()
243 		nvkm_falcon_mask(falcon, 0x004, 0xffffffff, irqsclr);  in gm200_flcn_fw_boot()
255 		nvkm_falcon_mask(falcon, 0x048, 0x00000001, 0x00000001);  in gm200_flcn_fw_load()
258 		case NVKM_MEM_TARGET_VRAM: target = 0; break;  in gm200_flcn_fw_load()
271 		) < 0)  in gm200_flcn_fw_load()
274 		nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008);  in gm200_flcn_fw_load()
275 		nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002);  in gm200_flcn_fw_load()
278 			if (falcon->func->bind_stat(falcon, false) == 0)  in gm200_flcn_fw_load()
280 		) < 0)  in gm200_flcn_fw_load()
283 		nvkm_falcon_mask(falcon, 0x624, 0x00000080, 0x00000080);  in gm200_flcn_fw_load()
284 		nvkm_falcon_wr32(falcon, 0x10c, 0x00000000);  in gm200_flcn_fw_load()
297 		ret = nvkm_falcon_pio_wr(falcon, fw->boot, 0, 0,  in gm200_flcn_fw_load()
306 	ret = nvkm_falcon_pio_wr(falcon, fw->fw.img + fw->nmem_base_img, fw->nmem_base_img, 0,  in gm200_flcn_fw_load()
311 	ret = nvkm_falcon_pio_wr(falcon, fw->fw.img + fw->imem_base_img, fw->imem_base_img, 0,  in gm200_flcn_fw_load()
316 	ret = nvkm_falcon_pio_wr(falcon, fw->fw.img + fw->dmem_base_img, fw->dmem_base_img, 0,  in gm200_flcn_fw_load()
317 				 DMEM, fw->dmem_base, fw->dmem_size, 0, false);  in gm200_flcn_fw_load()
321 	return 0;  in gm200_flcn_fw_load()
335 	int ret = 0;  in gm200_flcn_fw_signature()
342 		if (nvkm_falcon_rd32(falcon, addr) & 0x00100000) {  in gm200_flcn_fw_signature()