30 tu102_gr_init_fecs_exceptions(struct gf100_gr *gr)  in tu102_gr_init_fecs_exceptions()  argument
32 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003);  in tu102_gr_init_fecs_exceptions()
36 tu102_gr_init_fs(struct gf100_gr *gr)  in tu102_gr_init_fs()  argument
38 	struct nvkm_device *device = gr->base.engine.subdev.device;  in tu102_gr_init_fs()
41 	gp100_grctx_generate_smid_config(gr);  in tu102_gr_init_fs()
42 	gk104_grctx_generate_gpc_tpc_nr(gr);  in tu102_gr_init_fs()
44 	for (sm = 0; sm < gr->sm_nr; sm++) {  in tu102_gr_init_fs()
45 		int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc);  in tu102_gr_init_fs()
47 		nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm);  in tu102_gr_init_fs()
50 	gm200_grctx_generate_dist_skip_table(gr);  in tu102_gr_init_fs()
51 	gf100_gr_init_num_tpc_per_gpc(gr, true, true);  in tu102_gr_init_fs()
55 tu102_gr_init_zcull(struct gf100_gr *gr)  in tu102_gr_init_zcull()  argument
57 	struct nvkm_device *device = gr->base.engine.subdev.device;  in tu102_gr_init_zcull()
58 	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);  in tu102_gr_init_zcull()
59 	const u8 tile_nr = gr->func->gpc_nr * gr->func->tpc_nr;  in tu102_gr_init_zcull()
64 		for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {  in tu102_gr_init_zcull()
65 			data |= bank[gr->tile[i + j]] << (j * 4);  in tu102_gr_init_zcull()
66 			bank[gr->tile[i + j]]++;  in tu102_gr_init_zcull()
71 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {  in tu102_gr_init_zcull()
73 			  gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);  in tu102_gr_init_zcull()
75 							 gr->tpc_total);  in tu102_gr_init_zcull()
83 tu102_gr_init_gpc_mmu(struct gf100_gr *gr)  in tu102_gr_init_gpc_mmu()  argument
85 	struct nvkm_device *device = gr->base.engine.subdev.device;  in tu102_gr_init_gpc_mmu()