32 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003);  in tu102_gr_init_fecs_exceptions()
44 	for (sm = 0; sm < gr->sm_nr; sm++) {  in tu102_gr_init_fs()
47 		nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm);  in tu102_gr_init_fs()
58 	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);  in tu102_gr_init_zcull()
63 	for (i = 0; i < tile_nr; i += 8) {  in tu102_gr_init_zcull()
64 		for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {  in tu102_gr_init_zcull()
68 		nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);  in tu102_gr_init_zcull()
71 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {  in tu102_gr_init_zcull()
72 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),  in tu102_gr_init_zcull()
74 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |  in tu102_gr_init_zcull()
76 		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);  in tu102_gr_init_zcull()
79 	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);  in tu102_gr_init_zcull()
87 	nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);  in tu102_gr_init_gpc_mmu()
88 	nvkm_wr32(device, 0x418890, 0x00000000);  in tu102_gr_init_gpc_mmu()
89 	nvkm_wr32(device, 0x418894, 0x00000000);  in tu102_gr_init_gpc_mmu()
91 	nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));  in tu102_gr_init_gpc_mmu()
92 	nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));  in tu102_gr_init_gpc_mmu()
93 	nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));  in tu102_gr_init_gpc_mmu()
208 	return gk20a_gr_av_to_init_(blob, 64, 0x00100000, ppack);  in tu102_gr_av_to_init_veid()
213 	{  0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },