26 	return 0;  in nv20_gr_chan_init()
38 	nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);  in nv20_gr_chan_fini()
39 	if (nvkm_rd32(device, 0x400144) & 0x00010000)  in nv20_gr_chan_fini()
40 		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;  in nv20_gr_chan_fini()
42 		nvkm_wr32(device, 0x400784, inst >> 4);  in nv20_gr_chan_fini()
43 		nvkm_wr32(device, 0x400788, 0x00000002);  in nv20_gr_chan_fini()
45 			if (!nvkm_rd32(device, 0x400700))  in nv20_gr_chan_fini()
48 		nvkm_wr32(device, 0x400144, 0x10000000);  in nv20_gr_chan_fini()
49 		nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);  in nv20_gr_chan_fini()
51 	nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);  in nv20_gr_chan_fini()
54 	nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);  in nv20_gr_chan_fini()
56 	return 0;  in nv20_gr_chan_fini()
90 			      NVKM_MEM_TARGET_INST, 0x37f0, 16, true,  in nv20_gr_chan_new()
96 	nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));  in nv20_gr_chan_new()
97 	nvkm_wo32(chan->inst, 0x033c, 0xffff0000);  in nv20_gr_chan_new()
98 	nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);  in nv20_gr_chan_new()
99 	nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);  in nv20_gr_chan_new()
100 	nvkm_wo32(chan->inst, 0x047c, 0x00000101);  in nv20_gr_chan_new()
101 	nvkm_wo32(chan->inst, 0x0490, 0x00000111);  in nv20_gr_chan_new()
102 	nvkm_wo32(chan->inst, 0x04a8, 0x44400000);  in nv20_gr_chan_new()
103 	for (i = 0x04d4; i <= 0x04e0; i += 4)  in nv20_gr_chan_new()
104 		nvkm_wo32(chan->inst, i, 0x00030303);  in nv20_gr_chan_new()
105 	for (i = 0x04f4; i <= 0x0500; i += 4)  in nv20_gr_chan_new()
106 		nvkm_wo32(chan->inst, i, 0x00080000);  in nv20_gr_chan_new()
107 	for (i = 0x050c; i <= 0x0518; i += 4)  in nv20_gr_chan_new()
108 		nvkm_wo32(chan->inst, i, 0x01012000);  in nv20_gr_chan_new()
109 	for (i = 0x051c; i <= 0x0528; i += 4)  in nv20_gr_chan_new()
110 		nvkm_wo32(chan->inst, i, 0x000105b8);  in nv20_gr_chan_new()
111 	for (i = 0x052c; i <= 0x0538; i += 4)  in nv20_gr_chan_new()
112 		nvkm_wo32(chan->inst, i, 0x00080008);  in nv20_gr_chan_new()
113 	for (i = 0x055c; i <= 0x0598; i += 4)  in nv20_gr_chan_new()
114 		nvkm_wo32(chan->inst, i, 0x07ff0000);  in nv20_gr_chan_new()
115 	nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);  in nv20_gr_chan_new()
116 	nvkm_wo32(chan->inst, 0x05fc, 0x00000001);  in nv20_gr_chan_new()
117 	nvkm_wo32(chan->inst, 0x0604, 0x00004000);  in nv20_gr_chan_new()
118 	nvkm_wo32(chan->inst, 0x0610, 0x00000001);  in nv20_gr_chan_new()
119 	nvkm_wo32(chan->inst, 0x0618, 0x00040000);  in nv20_gr_chan_new()
120 	nvkm_wo32(chan->inst, 0x061c, 0x00010000);  in nv20_gr_chan_new()
121 	for (i = 0x1c1c; i <= 0x248c; i += 16) {  in nv20_gr_chan_new()
122 		nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);  in nv20_gr_chan_new()
123 		nvkm_wo32(chan->inst, (i + 4), 0x0436086c);  in nv20_gr_chan_new()
124 		nvkm_wo32(chan->inst, (i + 8), 0x000c001b);  in nv20_gr_chan_new()
126 	nvkm_wo32(chan->inst, 0x281c, 0x3f800000);  in nv20_gr_chan_new()
127 	nvkm_wo32(chan->inst, 0x2830, 0x3f800000);  in nv20_gr_chan_new()
128 	nvkm_wo32(chan->inst, 0x285c, 0x40000000);  in nv20_gr_chan_new()
129 	nvkm_wo32(chan->inst, 0x2860, 0x3f800000);  in nv20_gr_chan_new()
130 	nvkm_wo32(chan->inst, 0x2864, 0x3f000000);  in nv20_gr_chan_new()
131 	nvkm_wo32(chan->inst, 0x286c, 0x40000000);  in nv20_gr_chan_new()
132 	nvkm_wo32(chan->inst, 0x2870, 0x3f800000);  in nv20_gr_chan_new()
133 	nvkm_wo32(chan->inst, 0x2878, 0xbf800000);  in nv20_gr_chan_new()
134 	nvkm_wo32(chan->inst, 0x2880, 0xbf800000);  in nv20_gr_chan_new()
135 	nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);  in nv20_gr_chan_new()
136 	nvkm_wo32(chan->inst, 0x3530, 0x000003f8);  in nv20_gr_chan_new()
137 	nvkm_wo32(chan->inst, 0x3540, 0x002fe000);  in nv20_gr_chan_new()
138 	for (i = 0x355c; i <= 0x3578; i += 4)  in nv20_gr_chan_new()
139 		nvkm_wo32(chan->inst, i, 0x001c527c);  in nv20_gr_chan_new()
141 	return 0;  in nv20_gr_chan_new()
163 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);  in nv20_gr_tile()
165 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);  in nv20_gr_tile()
167 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);  in nv20_gr_tile()
170 	if (device->chipset != 0x34) {  in nv20_gr_tile()
172 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);  in nv20_gr_tile()
190 	u32 chid = (addr & 0x01f00000) >> 20;  in nv20_gr_intr()
191 	u32 subc = (addr & 0x00070000) >> 16;  in nv20_gr_intr()
192 	u32 mthd = (addr & 0x00001ffc);  in nv20_gr_intr()
194 	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;  in nv20_gr_intr()
202 	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);  in nv20_gr_intr()
239 	if (device->chipset == 0x20) {  in nv20_gr_init()
240 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);  in nv20_gr_init()
241 		for (i = 0; i < 15; i++)  in nv20_gr_init()
242 			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);  in nv20_gr_init()
244 			if (!nvkm_rd32(device, 0x400700))  in nv20_gr_init()
248 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);  in nv20_gr_init()
249 		for (i = 0; i < 32; i++)  in nv20_gr_init()
250 			nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);  in nv20_gr_init()
252 			if (!nvkm_rd32(device, 0x400700))  in nv20_gr_init()
257 	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);  in nv20_gr_init()
258 	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);  in nv20_gr_init()
260 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);  in nv20_gr_init()
261 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);  in nv20_gr_init()
262 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);  in nv20_gr_init()
263 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */  in nv20_gr_init()
264 	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);  in nv20_gr_init()
265 	nvkm_wr32(device, 0x40009C           , 0x00000040);  in nv20_gr_init()
267 	if (device->chipset >= 0x25) {  in nv20_gr_init()
268 		nvkm_wr32(device, 0x400890, 0x00a8cfff);  in nv20_gr_init()
269 		nvkm_wr32(device, 0x400610, 0x304B1FB6);  in nv20_gr_init()
270 		nvkm_wr32(device, 0x400B80, 0x1cbd3883);  in nv20_gr_init()
271 		nvkm_wr32(device, 0x400B84, 0x44000000);  in nv20_gr_init()
272 		nvkm_wr32(device, 0x400098, 0x40000080);  in nv20_gr_init()
273 		nvkm_wr32(device, 0x400B88, 0x000000ff);  in nv20_gr_init()
276 		nvkm_wr32(device, 0x400880, 0x0008c7df);  in nv20_gr_init()
277 		nvkm_wr32(device, 0x400094, 0x00000005);  in nv20_gr_init()
278 		nvkm_wr32(device, 0x400B80, 0x45eae20e);  in nv20_gr_init()
279 		nvkm_wr32(device, 0x400B84, 0x24000000);  in nv20_gr_init()
280 		nvkm_wr32(device, 0x400098, 0x00000040);  in nv20_gr_init()
281 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);  in nv20_gr_init()
282 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);  in nv20_gr_init()
283 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);  in nv20_gr_init()
284 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);  in nv20_gr_init()
287 	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));  in nv20_gr_init()
288 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);  in nv20_gr_init()
289 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));  in nv20_gr_init()
291 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);  in nv20_gr_init()
292 	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);  in nv20_gr_init()
294 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;  in nv20_gr_init()
296 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;  in nv20_gr_init()
301 	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));  in nv20_gr_init()
302 	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));  in nv20_gr_init()
303 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);  in nv20_gr_init()
304 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));  in nv20_gr_init()
305 	nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);  in nv20_gr_init()
306 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));  in nv20_gr_init()
307 	nvkm_wr32(device, 0x400820, 0);  in nv20_gr_init()
308 	nvkm_wr32(device, 0x400824, 0);  in nv20_gr_init()
309 	nvkm_wr32(device, 0x400864, vramsz - 1);  in nv20_gr_init()
310 	nvkm_wr32(device, 0x400868, vramsz - 1);  in nv20_gr_init()
313 	nvkm_wr32(device, 0x400B20, 0x00000000);  in nv20_gr_init()
314 	nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);  in nv20_gr_init()
316 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);  in nv20_gr_init()
317 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);  in nv20_gr_init()
318 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);  in nv20_gr_init()
319 	nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);  in nv20_gr_init()
320 	return 0;  in nv20_gr_init()
353 		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
354 		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
355 		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
356 		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
357 		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
358 		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
359 		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
360 		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
361 		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
362 		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
363 		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
364 		{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
365 		{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
366 		{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
367 		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */