Lines Matching +full:0 +full:x700000
36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
54 0x004001c8,
55 0x004001e8,
56 0x0040018c,
57 0x004001ac,
58 0x004001cc,
59 0x004001ec,
60 0x00400190,
61 0x004001b0,
62 0x004001d0,
63 0x004001f0,
64 0x00400194,
65 0x004001b4,
66 0x004001d4,
67 0x004001f4,
68 0x00400198,
69 0x004001b8,
70 0x004001d8,
71 0x004001f8,
72 0x0040019c,
73 0x004001bc,
74 0x004001dc,
75 0x004001fc,
76 0x00400174,
113 NV04_PGRAPH_PATT_COLORRAM+0x00,
114 NV04_PGRAPH_PATT_COLORRAM+0x04,
115 NV04_PGRAPH_PATT_COLORRAM+0x08,
116 NV04_PGRAPH_PATT_COLORRAM+0x0c,
117 NV04_PGRAPH_PATT_COLORRAM+0x10,
118 NV04_PGRAPH_PATT_COLORRAM+0x14,
119 NV04_PGRAPH_PATT_COLORRAM+0x18,
120 NV04_PGRAPH_PATT_COLORRAM+0x1c,
121 NV04_PGRAPH_PATT_COLORRAM+0x20,
122 NV04_PGRAPH_PATT_COLORRAM+0x24,
123 NV04_PGRAPH_PATT_COLORRAM+0x28,
124 NV04_PGRAPH_PATT_COLORRAM+0x2c,
125 NV04_PGRAPH_PATT_COLORRAM+0x30,
126 NV04_PGRAPH_PATT_COLORRAM+0x34,
127 NV04_PGRAPH_PATT_COLORRAM+0x38,
128 NV04_PGRAPH_PATT_COLORRAM+0x3c,
129 NV04_PGRAPH_PATT_COLORRAM+0x40,
130 NV04_PGRAPH_PATT_COLORRAM+0x44,
131 NV04_PGRAPH_PATT_COLORRAM+0x48,
132 NV04_PGRAPH_PATT_COLORRAM+0x4c,
133 NV04_PGRAPH_PATT_COLORRAM+0x50,
134 NV04_PGRAPH_PATT_COLORRAM+0x54,
135 NV04_PGRAPH_PATT_COLORRAM+0x58,
136 NV04_PGRAPH_PATT_COLORRAM+0x5c,
137 NV04_PGRAPH_PATT_COLORRAM+0x60,
138 NV04_PGRAPH_PATT_COLORRAM+0x64,
139 NV04_PGRAPH_PATT_COLORRAM+0x68,
140 NV04_PGRAPH_PATT_COLORRAM+0x6c,
141 NV04_PGRAPH_PATT_COLORRAM+0x70,
142 NV04_PGRAPH_PATT_COLORRAM+0x74,
143 NV04_PGRAPH_PATT_COLORRAM+0x78,
144 NV04_PGRAPH_PATT_COLORRAM+0x7c,
145 NV04_PGRAPH_PATT_COLORRAM+0x80,
146 NV04_PGRAPH_PATT_COLORRAM+0x84,
147 NV04_PGRAPH_PATT_COLORRAM+0x88,
148 NV04_PGRAPH_PATT_COLORRAM+0x8c,
149 NV04_PGRAPH_PATT_COLORRAM+0x90,
150 NV04_PGRAPH_PATT_COLORRAM+0x94,
151 NV04_PGRAPH_PATT_COLORRAM+0x98,
152 NV04_PGRAPH_PATT_COLORRAM+0x9c,
153 NV04_PGRAPH_PATT_COLORRAM+0xa0,
154 NV04_PGRAPH_PATT_COLORRAM+0xa4,
155 NV04_PGRAPH_PATT_COLORRAM+0xa8,
156 NV04_PGRAPH_PATT_COLORRAM+0xac,
157 NV04_PGRAPH_PATT_COLORRAM+0xb0,
158 NV04_PGRAPH_PATT_COLORRAM+0xb4,
159 NV04_PGRAPH_PATT_COLORRAM+0xb8,
160 NV04_PGRAPH_PATT_COLORRAM+0xbc,
161 NV04_PGRAPH_PATT_COLORRAM+0xc0,
162 NV04_PGRAPH_PATT_COLORRAM+0xc4,
163 NV04_PGRAPH_PATT_COLORRAM+0xc8,
164 NV04_PGRAPH_PATT_COLORRAM+0xcc,
165 NV04_PGRAPH_PATT_COLORRAM+0xd0,
166 NV04_PGRAPH_PATT_COLORRAM+0xd4,
167 NV04_PGRAPH_PATT_COLORRAM+0xd8,
168 NV04_PGRAPH_PATT_COLORRAM+0xdc,
169 NV04_PGRAPH_PATT_COLORRAM+0xe0,
170 NV04_PGRAPH_PATT_COLORRAM+0xe4,
171 NV04_PGRAPH_PATT_COLORRAM+0xe8,
172 NV04_PGRAPH_PATT_COLORRAM+0xec,
173 NV04_PGRAPH_PATT_COLORRAM+0xf0,
174 NV04_PGRAPH_PATT_COLORRAM+0xf4,
175 NV04_PGRAPH_PATT_COLORRAM+0xf8,
176 NV04_PGRAPH_PATT_COLORRAM+0xfc,
178 0x0040080c,
180 0x00400600,
191 0x00400560,
192 0x00400568,
193 0x00400564,
194 0x0040056c,
195 0x00400400,
196 0x00400480,
197 0x00400404,
198 0x00400484,
199 0x00400408,
200 0x00400488,
201 0x0040040c,
202 0x0040048c,
203 0x00400410,
204 0x00400490,
205 0x00400414,
206 0x00400494,
207 0x00400418,
208 0x00400498,
209 0x0040041c,
210 0x0040049c,
211 0x00400420,
212 0x004004a0,
213 0x00400424,
214 0x004004a4,
215 0x00400428,
216 0x004004a8,
217 0x0040042c,
218 0x004004ac,
219 0x00400430,
220 0x004004b0,
221 0x00400434,
222 0x004004b4,
223 0x00400438,
224 0x004004b8,
225 0x0040043c,
226 0x004004bc,
227 0x00400440,
228 0x004004c0,
229 0x00400444,
230 0x004004c4,
231 0x00400448,
232 0x004004c8,
233 0x0040044c,
234 0x004004cc,
235 0x00400450,
236 0x004004d0,
237 0x00400454,
238 0x004004d4,
239 0x00400458,
240 0x004004d8,
241 0x0040045c,
242 0x004004dc,
243 0x00400460,
244 0x004004e0,
245 0x00400464,
246 0x004004e4,
247 0x00400468,
248 0x004004e8,
249 0x0040046c,
250 0x004004ec,
251 0x00400470,
252 0x004004f0,
253 0x00400474,
254 0x004004f4,
255 0x00400478,
256 0x004004f8,
257 0x0040047c,
258 0x004004fc,
259 0x00400534,
260 0x00400538,
261 0x00400514,
262 0x00400518,
263 0x0040051c,
264 0x00400520,
265 0x00400524,
266 0x00400528,
267 0x0040052c,
268 0x00400530,
269 0x00400d00,
270 0x00400d40,
271 0x00400d80,
272 0x00400d04,
273 0x00400d44,
274 0x00400d84,
275 0x00400d08,
276 0x00400d48,
277 0x00400d88,
278 0x00400d0c,
279 0x00400d4c,
280 0x00400d8c,
281 0x00400d10,
282 0x00400d50,
283 0x00400d90,
284 0x00400d14,
285 0x00400d54,
286 0x00400d94,
287 0x00400d18,
288 0x00400d58,
289 0x00400d98,
290 0x00400d1c,
291 0x00400d5c,
292 0x00400d9c,
293 0x00400d20,
294 0x00400d60,
295 0x00400da0,
296 0x00400d24,
297 0x00400d64,
298 0x00400da4,
299 0x00400d28,
300 0x00400d68,
301 0x00400da8,
302 0x00400d2c,
303 0x00400d6c,
304 0x00400dac,
305 0x00400d30,
306 0x00400d70,
307 0x00400db0,
308 0x00400d34,
309 0x00400d74,
310 0x00400db4,
311 0x00400d38,
312 0x00400d78,
313 0x00400db8,
314 0x00400d3c,
315 0x00400d7c,
316 0x00400dbc,
317 0x00400590,
318 0x00400594,
319 0x00400598,
320 0x0040059c,
321 0x004005a8,
322 0x004005ac,
323 0x004005b0,
324 0x004005b4,
325 0x004005c0,
326 0x004005c4,
327 0x004005c8,
328 0x004005cc,
329 0x004005d0,
330 0x004005d4,
331 0x004005d8,
332 0x004005dc,
333 0x004005e0,
342 0x00400500,
343 0x00400504,
377 * word 0:
378 * - bits 0-7: class
383 * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
389 * - bits 0-1: mono format
393 * - bits 0-15: DMA_A instance
398 * word 0:
399 * - bits 0-7: class
404 * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
416 * - bits 0-1: mono format
420 * - bits 0-15: DMA_A instance
447 int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; in nv04_gr_set_ctx1()
450 tmp = nvkm_rd32(device, 0x700000 + inst); in nv04_gr_set_ctx1()
453 nvkm_wr32(device, 0x700000 + inst, tmp); in nv04_gr_set_ctx1()
465 ctx1 = nvkm_rd32(device, 0x700000 + inst); in nv04_gr_set_ctx_val()
466 class = ctx1 & 0xff; in nv04_gr_set_ctx_val()
469 tmp = nvkm_rd32(device, 0x70000c + inst); in nv04_gr_set_ctx_val()
472 nvkm_wr32(device, 0x70000c + inst, tmp); in nv04_gr_set_ctx_val()
475 if (!(tmp & 0x02000000)) in nv04_gr_set_ctx_val()
476 valid = 0; in nv04_gr_set_ctx_val()
478 if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000)) in nv04_gr_set_ctx_val()
479 valid = 0; in nv04_gr_set_ctx_val()
483 case 0: in nv04_gr_set_ctx_val()
488 if (!(tmp & 0x18000000)) in nv04_gr_set_ctx_val()
489 valid = 0; in nv04_gr_set_ctx_val()
493 if (!(tmp & 0x20000000)) in nv04_gr_set_ctx_val()
494 valid = 0; in nv04_gr_set_ctx_val()
499 if (!(tmp & 0x40000000)) in nv04_gr_set_ctx_val()
500 valid = 0; in nv04_gr_set_ctx_val()
504 nv04_gr_set_ctx1(device, inst, 0x01000000, valid << 24); in nv04_gr_set_ctx_val()
510 u8 class = nvkm_rd32(device, 0x700000) & 0x000000ff; in nv04_gr_mthd_set_operation()
514 if (data > 2 && class < 0x40) in nv04_gr_mthd_set_operation()
516 nv04_gr_set_ctx1(device, inst, 0x00038000, data << 15); in nv04_gr_mthd_set_operation()
518 nv04_gr_set_ctx_val(device, inst, 0, 0); in nv04_gr_mthd_set_operation()
525 u32 min = data & 0xffff, max; in nv04_gr_mthd_surf3d_clip_h()
527 if (min & 0x8000) in nv04_gr_mthd_surf3d_clip_h()
530 if (w & 0x8000) in nv04_gr_mthd_surf3d_clip_h()
532 w |= 0xffff0000; in nv04_gr_mthd_surf3d_clip_h()
534 max &= 0x3ffff; in nv04_gr_mthd_surf3d_clip_h()
535 nvkm_wr32(device, 0x40053c, min); in nv04_gr_mthd_surf3d_clip_h()
536 nvkm_wr32(device, 0x400544, max); in nv04_gr_mthd_surf3d_clip_h()
543 u32 min = data & 0xffff, max; in nv04_gr_mthd_surf3d_clip_v()
545 if (min & 0x8000) in nv04_gr_mthd_surf3d_clip_v()
548 if (w & 0x8000) in nv04_gr_mthd_surf3d_clip_v()
550 w |= 0xffff0000; in nv04_gr_mthd_surf3d_clip_v()
552 max &= 0x3ffff; in nv04_gr_mthd_surf3d_clip_v()
553 nvkm_wr32(device, 0x400540, min); in nv04_gr_mthd_surf3d_clip_v()
554 nvkm_wr32(device, 0x400548, max); in nv04_gr_mthd_surf3d_clip_v()
561 return nvkm_rd32(device, 0x700000 + (inst << 4)); in nv04_gr_mthd_bind_class()
568 case 0x30: in nv04_gr_mthd_bind_surf2d()
569 nv04_gr_set_ctx1(device, inst, 0x00004000, 0); in nv04_gr_mthd_bind_surf2d()
570 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); in nv04_gr_mthd_bind_surf2d()
572 case 0x42: in nv04_gr_mthd_bind_surf2d()
573 nv04_gr_set_ctx1(device, inst, 0x00004000, 0); in nv04_gr_mthd_bind_surf2d()
574 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); in nv04_gr_mthd_bind_surf2d()
584 case 0x30: in nv04_gr_mthd_bind_surf2d_swzsurf()
585 nv04_gr_set_ctx1(device, inst, 0x00004000, 0); in nv04_gr_mthd_bind_surf2d_swzsurf()
586 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); in nv04_gr_mthd_bind_surf2d_swzsurf()
588 case 0x42: in nv04_gr_mthd_bind_surf2d_swzsurf()
589 nv04_gr_set_ctx1(device, inst, 0x00004000, 0); in nv04_gr_mthd_bind_surf2d_swzsurf()
590 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); in nv04_gr_mthd_bind_surf2d_swzsurf()
592 case 0x52: in nv04_gr_mthd_bind_surf2d_swzsurf()
593 nv04_gr_set_ctx1(device, inst, 0x00004000, 0x00004000); in nv04_gr_mthd_bind_surf2d_swzsurf()
594 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); in nv04_gr_mthd_bind_surf2d_swzsurf()
604 case 0x30: in nv01_gr_mthd_bind_patt()
605 nv04_gr_set_ctx_val(device, inst, 0x08000000, 0); in nv01_gr_mthd_bind_patt()
607 case 0x18: in nv01_gr_mthd_bind_patt()
608 nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000); in nv01_gr_mthd_bind_patt()
618 case 0x30: in nv04_gr_mthd_bind_patt()
619 nv04_gr_set_ctx_val(device, inst, 0x08000000, 0); in nv04_gr_mthd_bind_patt()
621 case 0x44: in nv04_gr_mthd_bind_patt()
622 nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000); in nv04_gr_mthd_bind_patt()
632 case 0x30: in nv04_gr_mthd_bind_rop()
633 nv04_gr_set_ctx_val(device, inst, 0x10000000, 0); in nv04_gr_mthd_bind_rop()
635 case 0x43: in nv04_gr_mthd_bind_rop()
636 nv04_gr_set_ctx_val(device, inst, 0x10000000, 0x10000000); in nv04_gr_mthd_bind_rop()
646 case 0x30: in nv04_gr_mthd_bind_beta1()
647 nv04_gr_set_ctx_val(device, inst, 0x20000000, 0); in nv04_gr_mthd_bind_beta1()
649 case 0x12: in nv04_gr_mthd_bind_beta1()
650 nv04_gr_set_ctx_val(device, inst, 0x20000000, 0x20000000); in nv04_gr_mthd_bind_beta1()
660 case 0x30: in nv04_gr_mthd_bind_beta4()
661 nv04_gr_set_ctx_val(device, inst, 0x40000000, 0); in nv04_gr_mthd_bind_beta4()
663 case 0x72: in nv04_gr_mthd_bind_beta4()
664 nv04_gr_set_ctx_val(device, inst, 0x40000000, 0x40000000); in nv04_gr_mthd_bind_beta4()
674 case 0x30: in nv04_gr_mthd_bind_surf_dst()
675 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); in nv04_gr_mthd_bind_surf_dst()
677 case 0x58: in nv04_gr_mthd_bind_surf_dst()
678 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); in nv04_gr_mthd_bind_surf_dst()
688 case 0x30: in nv04_gr_mthd_bind_surf_src()
689 nv04_gr_set_ctx_val(device, inst, 0x04000000, 0); in nv04_gr_mthd_bind_surf_src()
691 case 0x59: in nv04_gr_mthd_bind_surf_src()
692 nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000); in nv04_gr_mthd_bind_surf_src()
702 case 0x30: in nv04_gr_mthd_bind_surf_color()
703 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); in nv04_gr_mthd_bind_surf_color()
705 case 0x5a: in nv04_gr_mthd_bind_surf_color()
706 nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); in nv04_gr_mthd_bind_surf_color()
716 case 0x30: in nv04_gr_mthd_bind_surf_zeta()
717 nv04_gr_set_ctx_val(device, inst, 0x04000000, 0); in nv04_gr_mthd_bind_surf_zeta()
719 case 0x5b: in nv04_gr_mthd_bind_surf_zeta()
720 nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000); in nv04_gr_mthd_bind_surf_zeta()
730 case 0x30: in nv01_gr_mthd_bind_clip()
731 nv04_gr_set_ctx1(device, inst, 0x2000, 0); in nv01_gr_mthd_bind_clip()
733 case 0x19: in nv01_gr_mthd_bind_clip()
734 nv04_gr_set_ctx1(device, inst, 0x2000, 0x2000); in nv01_gr_mthd_bind_clip()
744 case 0x30: in nv01_gr_mthd_bind_chroma()
745 nv04_gr_set_ctx1(device, inst, 0x1000, 0); in nv01_gr_mthd_bind_chroma()
748 * accept 0x57 and not 0x17. Consistency be damned. in nv01_gr_mthd_bind_chroma()
750 case 0x57: in nv01_gr_mthd_bind_chroma()
751 nv04_gr_set_ctx1(device, inst, 0x1000, 0x1000); in nv01_gr_mthd_bind_chroma()
762 case 0x0184: func = nv01_gr_mthd_bind_patt; break; in nv03_gr_mthd_gdi()
763 case 0x0188: func = nv04_gr_mthd_bind_rop; break; in nv03_gr_mthd_gdi()
764 case 0x018c: func = nv04_gr_mthd_bind_beta1; break; in nv03_gr_mthd_gdi()
765 case 0x0190: func = nv04_gr_mthd_bind_surf_dst; break; in nv03_gr_mthd_gdi()
766 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv03_gr_mthd_gdi()
778 case 0x0188: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_gdi()
779 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_gdi()
780 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_gdi()
781 case 0x0194: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_gdi()
782 case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; in nv04_gr_mthd_gdi()
783 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_gdi()
795 case 0x0184: func = nv01_gr_mthd_bind_chroma; break; in nv01_gr_mthd_blit()
796 case 0x0188: func = nv01_gr_mthd_bind_clip; break; in nv01_gr_mthd_blit()
797 case 0x018c: func = nv01_gr_mthd_bind_patt; break; in nv01_gr_mthd_blit()
798 case 0x0190: func = nv04_gr_mthd_bind_rop; break; in nv01_gr_mthd_blit()
799 case 0x0194: func = nv04_gr_mthd_bind_beta1; break; in nv01_gr_mthd_blit()
800 case 0x0198: func = nv04_gr_mthd_bind_surf_dst; break; in nv01_gr_mthd_blit()
801 case 0x019c: func = nv04_gr_mthd_bind_surf_src; break; in nv01_gr_mthd_blit()
802 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv01_gr_mthd_blit()
814 case 0x0184: func = nv01_gr_mthd_bind_chroma; break; in nv04_gr_mthd_blit()
815 case 0x0188: func = nv01_gr_mthd_bind_clip; break; in nv04_gr_mthd_blit()
816 case 0x018c: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_blit()
817 case 0x0190: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_blit()
818 case 0x0194: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_blit()
819 case 0x0198: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_blit()
820 case 0x019c: func = nv04_gr_mthd_bind_surf2d; break; in nv04_gr_mthd_blit()
821 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_blit()
833 case 0x0188: func = nv01_gr_mthd_bind_chroma; break; in nv04_gr_mthd_iifc()
834 case 0x018c: func = nv01_gr_mthd_bind_clip; break; in nv04_gr_mthd_iifc()
835 case 0x0190: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_iifc()
836 case 0x0194: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_iifc()
837 case 0x0198: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_iifc()
838 case 0x019c: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_iifc()
839 case 0x01a0: func = nv04_gr_mthd_bind_surf2d_swzsurf; break; in nv04_gr_mthd_iifc()
840 case 0x03e4: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_iifc()
852 case 0x0184: func = nv01_gr_mthd_bind_chroma; break; in nv01_gr_mthd_ifc()
853 case 0x0188: func = nv01_gr_mthd_bind_clip; break; in nv01_gr_mthd_ifc()
854 case 0x018c: func = nv01_gr_mthd_bind_patt; break; in nv01_gr_mthd_ifc()
855 case 0x0190: func = nv04_gr_mthd_bind_rop; break; in nv01_gr_mthd_ifc()
856 case 0x0194: func = nv04_gr_mthd_bind_beta1; break; in nv01_gr_mthd_ifc()
857 case 0x0198: func = nv04_gr_mthd_bind_surf_dst; break; in nv01_gr_mthd_ifc()
858 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv01_gr_mthd_ifc()
870 case 0x0184: func = nv01_gr_mthd_bind_chroma; break; in nv04_gr_mthd_ifc()
871 case 0x0188: func = nv01_gr_mthd_bind_clip; break; in nv04_gr_mthd_ifc()
872 case 0x018c: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_ifc()
873 case 0x0190: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_ifc()
874 case 0x0194: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_ifc()
875 case 0x0198: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_ifc()
876 case 0x019c: func = nv04_gr_mthd_bind_surf2d; break; in nv04_gr_mthd_ifc()
877 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_ifc()
889 case 0x0184: func = nv01_gr_mthd_bind_chroma; break; in nv03_gr_mthd_sifc()
890 case 0x0188: func = nv01_gr_mthd_bind_patt; break; in nv03_gr_mthd_sifc()
891 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv03_gr_mthd_sifc()
892 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv03_gr_mthd_sifc()
893 case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break; in nv03_gr_mthd_sifc()
894 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv03_gr_mthd_sifc()
906 case 0x0184: func = nv01_gr_mthd_bind_chroma; break; in nv04_gr_mthd_sifc()
907 case 0x0188: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_sifc()
908 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_sifc()
909 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_sifc()
910 case 0x0194: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_sifc()
911 case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; in nv04_gr_mthd_sifc()
912 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_sifc()
924 case 0x0188: func = nv01_gr_mthd_bind_patt; break; in nv03_gr_mthd_sifm()
925 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv03_gr_mthd_sifm()
926 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv03_gr_mthd_sifm()
927 case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break; in nv03_gr_mthd_sifm()
928 case 0x0304: func = nv04_gr_mthd_set_operation; break; in nv03_gr_mthd_sifm()
940 case 0x0188: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_sifm()
941 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_sifm()
942 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_sifm()
943 case 0x0194: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_sifm()
944 case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; in nv04_gr_mthd_sifm()
945 case 0x0304: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_sifm()
957 case 0x02f8: func = nv04_gr_mthd_surf3d_clip_h; break; in nv04_gr_mthd_surf3d()
958 case 0x02fc: func = nv04_gr_mthd_surf3d_clip_v; break; in nv04_gr_mthd_surf3d()
970 case 0x0188: func = nv01_gr_mthd_bind_clip; break; in nv03_gr_mthd_ttri()
971 case 0x018c: func = nv04_gr_mthd_bind_surf_color; break; in nv03_gr_mthd_ttri()
972 case 0x0190: func = nv04_gr_mthd_bind_surf_zeta; break; in nv03_gr_mthd_ttri()
984 case 0x0184: func = nv01_gr_mthd_bind_clip; break; in nv01_gr_mthd_prim()
985 case 0x0188: func = nv01_gr_mthd_bind_patt; break; in nv01_gr_mthd_prim()
986 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv01_gr_mthd_prim()
987 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv01_gr_mthd_prim()
988 case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break; in nv01_gr_mthd_prim()
989 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv01_gr_mthd_prim()
1001 case 0x0184: func = nv01_gr_mthd_bind_clip; break; in nv04_gr_mthd_prim()
1002 case 0x0188: func = nv04_gr_mthd_bind_patt; break; in nv04_gr_mthd_prim()
1003 case 0x018c: func = nv04_gr_mthd_bind_rop; break; in nv04_gr_mthd_prim()
1004 case 0x0190: func = nv04_gr_mthd_bind_beta1; break; in nv04_gr_mthd_prim()
1005 case 0x0194: func = nv04_gr_mthd_bind_beta4; break; in nv04_gr_mthd_prim()
1006 case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; in nv04_gr_mthd_prim()
1007 case 0x02fc: func = nv04_gr_mthd_set_operation; break; in nv04_gr_mthd_prim()
1018 switch (nvkm_rd32(device, 0x700000 + inst) & 0x000000ff) { in nv04_gr_mthd()
1019 case 0x1c ... 0x1e: in nv04_gr_mthd()
1021 case 0x1f: func = nv01_gr_mthd_blit; break; in nv04_gr_mthd()
1022 case 0x21: func = nv01_gr_mthd_ifc; break; in nv04_gr_mthd()
1023 case 0x36: func = nv03_gr_mthd_sifc; break; in nv04_gr_mthd()
1024 case 0x37: func = nv03_gr_mthd_sifm; break; in nv04_gr_mthd()
1025 case 0x48: func = nv03_gr_mthd_ttri; break; in nv04_gr_mthd()
1026 case 0x4a: func = nv04_gr_mthd_gdi; break; in nv04_gr_mthd()
1027 case 0x4b: func = nv03_gr_mthd_gdi; break; in nv04_gr_mthd()
1028 case 0x53: func = nv04_gr_mthd_surf3d; break; in nv04_gr_mthd()
1029 case 0x5c ... 0x5e: in nv04_gr_mthd()
1031 case 0x5f: func = nv04_gr_mthd_blit; break; in nv04_gr_mthd()
1032 case 0x60: func = nv04_gr_mthd_iifc; break; in nv04_gr_mthd()
1033 case 0x61: func = nv04_gr_mthd_ifc; break; in nv04_gr_mthd()
1034 case 0x76: func = nv04_gr_mthd_sifc; break; in nv04_gr_mthd()
1035 case 0x77: func = nv04_gr_mthd_sifm; break; in nv04_gr_mthd()
1048 if (ret == 0) { in nv04_gr_object_bind()
1050 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv04_gr_object_bind()
1052 nvkm_mo32(*pgpuobj, 0x00, 0x00080000, 0x00080000); in nv04_gr_object_bind()
1054 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv04_gr_object_bind()
1055 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv04_gr_object_bind()
1056 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv04_gr_object_bind()
1076 if (nvkm_rd32(device, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { in nv04_gr_channel()
1090 for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) in nv04_gr_load_context()
1093 nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10010100); in nv04_gr_load_context()
1094 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv04_gr_load_context()
1095 nvkm_mask(device, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); in nv04_gr_load_context()
1096 return 0; in nv04_gr_load_context()
1105 for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) in nv04_gr_unload_context()
1108 nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10000000); in nv04_gr_unload_context()
1109 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); in nv04_gr_unload_context()
1110 return 0; in nv04_gr_unload_context()
1129 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; in nv04_gr_context_switch()
1139 for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) { in ctx_reg()
1169 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv04_gr_chan_fini()
1172 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv04_gr_chan_fini()
1174 return 0; in nv04_gr_chan_fini()
1198 *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; in nv04_gr_chan_new()
1203 return 0; in nv04_gr_chan_new()
1215 u32 mask = 0xffffffff; in nv04_gr_idle()
1223 ) < 0) { in nv04_gr_idle()
1281 u32 chid = (addr & 0x0f000000) >> 24; in nv04_gr_intr()
1282 u32 subc = (addr & 0x0000e000) >> 13; in nv04_gr_intr()
1283 u32 mthd = (addr & 0x00001ffc); in nv04_gr_intr()
1285 u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff; in nv04_gr_intr()
1286 u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4; in nv04_gr_intr()
1310 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); in nv04_gr_intr()
1334 nvkm_wr32(device, NV03_PGRAPH_INTR, 0xFFFFFFFF); in nv04_gr_init()
1335 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv04_gr_init()
1337 nvkm_wr32(device, NV04_PGRAPH_VALID1, 0); in nv04_gr_init()
1338 nvkm_wr32(device, NV04_PGRAPH_VALID2, 0); in nv04_gr_init()
1339 /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x000001FF); in nv04_gr_init()
1340 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ in nv04_gr_init()
1341 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x1231c000); in nv04_gr_init()
1343 /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ in nv04_gr_init()
1344 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x72111100); in nv04_gr_init()
1345 /*0x72111100 blob , 01 haiku*/ in nv04_gr_init()
1346 /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ in nv04_gr_init()
1347 nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f071); in nv04_gr_init()
1350 /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ in nv04_gr_init()
1351 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); in nv04_gr_init()
1354 nvkm_wr32(device, NV04_PGRAPH_STATE , 0xFFFFFFFF); in nv04_gr_init()
1355 nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL , 0x10000100); in nv04_gr_init()
1356 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); in nv04_gr_init()
1359 nvkm_wr32(device, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); in nv04_gr_init()
1360 nvkm_wr32(device, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); in nv04_gr_init()
1361 return 0; in nv04_gr_init()
1370 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
1371 { -1, -1, 0x0017, &nv04_gr_object }, /* chroma */
1372 { -1, -1, 0x0018, &nv04_gr_object }, /* pattern (nv01) */
1373 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
1374 { -1, -1, 0x001c, &nv04_gr_object }, /* line */
1375 { -1, -1, 0x001d, &nv04_gr_object }, /* tri */
1376 { -1, -1, 0x001e, &nv04_gr_object }, /* rect */
1377 { -1, -1, 0x001f, &nv04_gr_object },
1378 { -1, -1, 0x0021, &nv04_gr_object },
1379 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
1380 { -1, -1, 0x0036, &nv04_gr_object },
1381 { -1, -1, 0x0037, &nv04_gr_object },
1382 { -1, -1, 0x0038, &nv04_gr_object }, /* dvd subpicture */
1383 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
1384 { -1, -1, 0x0042, &nv04_gr_object }, /* surf2d */
1385 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
1386 { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
1387 { -1, -1, 0x0048, &nv04_gr_object },
1388 { -1, -1, 0x004a, &nv04_gr_object },
1389 { -1, -1, 0x004b, &nv04_gr_object },
1390 { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
1391 { -1, -1, 0x0053, &nv04_gr_object },
1392 { -1, -1, 0x0054, &nv04_gr_object }, /* ttri */
1393 { -1, -1, 0x0055, &nv04_gr_object }, /* mtri */
1394 { -1, -1, 0x0057, &nv04_gr_object }, /* chroma */
1395 { -1, -1, 0x0058, &nv04_gr_object }, /* surf_dst */
1396 { -1, -1, 0x0059, &nv04_gr_object }, /* surf_src */
1397 { -1, -1, 0x005a, &nv04_gr_object }, /* surf_color */
1398 { -1, -1, 0x005b, &nv04_gr_object }, /* surf_zeta */
1399 { -1, -1, 0x005c, &nv04_gr_object }, /* line */
1400 { -1, -1, 0x005d, &nv04_gr_object }, /* tri */
1401 { -1, -1, 0x005e, &nv04_gr_object }, /* rect */
1402 { -1, -1, 0x005f, &nv04_gr_object },
1403 { -1, -1, 0x0060, &nv04_gr_object },
1404 { -1, -1, 0x0061, &nv04_gr_object },
1405 { -1, -1, 0x0064, &nv04_gr_object }, /* iifc (nv05) */
1406 { -1, -1, 0x0065, &nv04_gr_object }, /* ifc (nv05) */
1407 { -1, -1, 0x0066, &nv04_gr_object }, /* sifc (nv05) */
1408 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
1409 { -1, -1, 0x0076, &nv04_gr_object },
1410 { -1, -1, 0x0077, &nv04_gr_object },