33 gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)  in gp100_gr_zbc_clear_color()  argument
35 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gp100_gr_zbc_clear_color()
39 	if (gr->zbc_color[zbc].format) {  in gp100_gr_zbc_clear_color()
40 		nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]);  in gp100_gr_zbc_clear_color()
41 		nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]);  in gp100_gr_zbc_clear_color()
42 		nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]);  in gp100_gr_zbc_clear_color()
43 		nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]);  in gp100_gr_zbc_clear_color()
48 			  gr->zbc_color[zbc].format << ((znum % 4) * 7));  in gp100_gr_zbc_clear_color()
52 gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)  in gp100_gr_zbc_clear_depth()  argument
54 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gp100_gr_zbc_clear_depth()
58 	if (gr->zbc_depth[zbc].format)  in gp100_gr_zbc_clear_depth()
59 		nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds);  in gp100_gr_zbc_clear_depth()
62 			  gr->zbc_depth[zbc].format << ((znum % 4) * 7));  in gp100_gr_zbc_clear_depth()
72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)  in gp100_gr_init_shader_exceptions()  argument
74 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gp100_gr_init_shader_exceptions()
80 gp100_gr_init_419c9c(struct gf100_gr *gr)  in gp100_gr_init_419c9c()  argument
82 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gp100_gr_init_419c9c()
88 gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)  in gp100_gr_init_fecs_exceptions()  argument
90 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000e0002);  in gp100_gr_init_fecs_exceptions()
94 gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)  in gp100_gr_init_rop_active_fbps()  argument
96 	struct nvkm_device *device = gr->base.engine.subdev.device;  in gp100_gr_init_rop_active_fbps()