40 		nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]);  in gp100_gr_zbc_clear_color()
41 		nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]);  in gp100_gr_zbc_clear_color()
42 		nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]);  in gp100_gr_zbc_clear_color()
43 		nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]);  in gp100_gr_zbc_clear_color()
46 	nvkm_mask(device, 0x418100 + ((znum / 4) * 4),  in gp100_gr_zbc_clear_color()
47 			  0x0000007f << ((znum % 4) * 7),  in gp100_gr_zbc_clear_color()
59 		nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds);  in gp100_gr_zbc_clear_depth()
60 	nvkm_mask(device, 0x41814c + ((znum / 4) * 4),  in gp100_gr_zbc_clear_depth()
61 			  0x0000007f << ((znum % 4) * 7),  in gp100_gr_zbc_clear_depth()
75 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);  in gp100_gr_init_shader_exceptions()
76 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);  in gp100_gr_init_shader_exceptions()
83 	nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);  in gp100_gr_init_419c9c()
84 	nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);  in gp100_gr_init_419c9c()
90 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000e0002);  in gp100_gr_init_fecs_exceptions()
98 	const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f;  in gp100_gr_init_rop_active_fbps()
99 	nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */  in gp100_gr_init_rop_active_fbps()
100 	nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */  in gp100_gr_init_rop_active_fbps()
156 	{  0, gm200_gr_load, &gp100_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },