Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
51 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_color()
52 if (gr->zbc_color[zbc].format) { in gf100_gr_zbc_clear_color()
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_color_get()
68 int zbc = -ENOSPC, i; in gf100_gr_zbc_color_get()
70 for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++) { in gf100_gr_zbc_color_get()
71 if (gr->zbc_color[i].format) { in gf100_gr_zbc_color_get()
72 if (gr->zbc_color[i].format != format) in gf100_gr_zbc_color_get()
74 if (memcmp(gr->zbc_color[i].ds, ds, sizeof( in gf100_gr_zbc_color_get()
75 gr->zbc_color[i].ds))) in gf100_gr_zbc_color_get()
77 if (memcmp(gr->zbc_color[i].l2, l2, sizeof( in gf100_gr_zbc_color_get()
78 gr->zbc_color[i].l2))) { in gf100_gr_zbc_color_get()
80 return -EINVAL; in gf100_gr_zbc_color_get()
84 zbc = (zbc < 0) ? i : zbc; in gf100_gr_zbc_color_get()
88 if (zbc < 0) in gf100_gr_zbc_color_get()
91 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); in gf100_gr_zbc_color_get()
92 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); in gf100_gr_zbc_color_get()
93 gr->zbc_color[zbc].format = format; in gf100_gr_zbc_color_get()
95 gr->func->zbc->clear_color(gr, zbc); in gf100_gr_zbc_color_get()
102 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_depth()
103 if (gr->zbc_depth[zbc].format) in gf100_gr_zbc_clear_depth()
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
106 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ in gf100_gr_zbc_clear_depth()
114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_depth_get()
115 int zbc = -ENOSPC, i; in gf100_gr_zbc_depth_get()
117 for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) { in gf100_gr_zbc_depth_get()
118 if (gr->zbc_depth[i].format) { in gf100_gr_zbc_depth_get()
119 if (gr->zbc_depth[i].format != format) in gf100_gr_zbc_depth_get()
121 if (gr->zbc_depth[i].ds != ds) in gf100_gr_zbc_depth_get()
123 if (gr->zbc_depth[i].l2 != l2) { in gf100_gr_zbc_depth_get()
125 return -EINVAL; in gf100_gr_zbc_depth_get()
129 zbc = (zbc < 0) ? i : zbc; in gf100_gr_zbc_depth_get()
133 if (zbc < 0) in gf100_gr_zbc_depth_get()
136 gr->zbc_depth[zbc].format = format; in gf100_gr_zbc_depth_get()
137 gr->zbc_depth[zbc].ds = ds; in gf100_gr_zbc_depth_get()
138 gr->zbc_depth[zbc].l2 = l2; in gf100_gr_zbc_depth_get()
140 gr->func->zbc->clear_depth(gr, zbc); in gf100_gr_zbc_depth_get()
163 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); in gf100_fermi_mthd_zbc_color()
167 int ret = -ENOSYS; in gf100_fermi_mthd_zbc_color()
169 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in gf100_fermi_mthd_zbc_color()
170 switch (args->v0.format) { in gf100_fermi_mthd_zbc_color()
190 ret = gf100_gr_zbc_color_get(gr, args->v0.format, in gf100_fermi_mthd_zbc_color()
191 args->v0.ds, in gf100_fermi_mthd_zbc_color()
192 args->v0.l2); in gf100_fermi_mthd_zbc_color()
193 if (ret >= 0) { in gf100_fermi_mthd_zbc_color()
194 args->v0.index = ret; in gf100_fermi_mthd_zbc_color()
195 return 0; in gf100_fermi_mthd_zbc_color()
199 return -EINVAL; in gf100_fermi_mthd_zbc_color()
209 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); in gf100_fermi_mthd_zbc_depth()
213 int ret = -ENOSYS; in gf100_fermi_mthd_zbc_depth()
215 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in gf100_fermi_mthd_zbc_depth()
216 switch (args->v0.format) { in gf100_fermi_mthd_zbc_depth()
218 ret = gf100_gr_zbc_depth_get(gr, args->v0.format, in gf100_fermi_mthd_zbc_depth()
219 args->v0.ds, in gf100_fermi_mthd_zbc_depth()
220 args->v0.l2); in gf100_fermi_mthd_zbc_depth()
221 return (ret >= 0) ? 0 : -ENOSPC; in gf100_fermi_mthd_zbc_depth()
223 return -EINVAL; in gf100_fermi_mthd_zbc_depth()
242 return -EINVAL; in gf100_fermi_mthd()
253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); in gf100_gr_mthd_set_shader_exceptions()
254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); in gf100_gr_mthd_set_shader_exceptions()
260 switch (class & 0x00ff) { in gf100_gr_mthd_sw()
261 case 0x97: in gf100_gr_mthd_sw()
262 case 0xc0: in gf100_gr_mthd_sw()
264 case 0x1528: in gf100_gr_mthd_sw()
285 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); in gf100_gr_object_new()
289 return -ENOMEM; in gf100_gr_object_new()
290 *pobject = &object->object; in gf100_gr_object_new()
292 nvkm_object_ctor(oclass->base.func ? oclass->base.func : in gf100_gr_object_new()
293 &gf100_gr_object_func, oclass, &object->object); in gf100_gr_object_new()
294 object->chan = chan; in gf100_gr_object_new()
295 return 0; in gf100_gr_object_new()
302 int c = 0; in gf100_gr_object_get()
304 while (gr->func->sclass[c].oclass) { in gf100_gr_object_get()
306 *sclass = gr->func->sclass[index]; in gf100_gr_object_get()
307 sclass->ctor = gf100_gr_object_new; in gf100_gr_object_get()
324 struct gf100_gr *gr = chan->gr; in gf100_gr_chan_bind()
327 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in gf100_gr_chan_bind()
333 for (i = 0; i < gr->size; i += 4) in gf100_gr_chan_bind()
334 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); in gf100_gr_chan_bind()
336 if (!gr->firmware) { in gf100_gr_chan_bind()
337 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); in gf100_gr_chan_bind()
338 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8); in gf100_gr_chan_bind()
340 nvkm_wo32(*pgpuobj, 0xf4, 0); in gf100_gr_chan_bind()
341 nvkm_wo32(*pgpuobj, 0xf8, 0); in gf100_gr_chan_bind()
342 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); in gf100_gr_chan_bind()
343 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr)); in gf100_gr_chan_bind()
344 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr)); in gf100_gr_chan_bind()
345 nvkm_wo32(*pgpuobj, 0x1c, 1); in gf100_gr_chan_bind()
346 nvkm_wo32(*pgpuobj, 0x20, 0); in gf100_gr_chan_bind()
347 nvkm_wo32(*pgpuobj, 0x28, 0); in gf100_gr_chan_bind()
348 nvkm_wo32(*pgpuobj, 0x2c, 0); in gf100_gr_chan_bind()
351 return 0; in gf100_gr_chan_bind()
359 nvkm_vmm_put(chan->vmm, &chan->mmio_vma); in gf100_gr_chan_dtor()
360 nvkm_memory_unref(&chan->mmio); in gf100_gr_chan_dtor()
362 nvkm_vmm_put(chan->vmm, &chan->attrib_cb); in gf100_gr_chan_dtor()
363 nvkm_vmm_put(chan->vmm, &chan->unknown); in gf100_gr_chan_dtor()
364 nvkm_vmm_put(chan->vmm, &chan->bundle_cb); in gf100_gr_chan_dtor()
365 nvkm_vmm_put(chan->vmm, &chan->pagepool); in gf100_gr_chan_dtor()
366 nvkm_vmm_unref(&chan->vmm); in gf100_gr_chan_dtor()
384 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_chan_new()
388 return -ENOMEM; in gf100_gr_chan_new()
389 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); in gf100_gr_chan_new()
390 chan->gr = gr; in gf100_gr_chan_new()
391 chan->vmm = nvkm_vmm_ref(fifoch->vmm); in gf100_gr_chan_new()
392 *pobject = &chan->object; in gf100_gr_chan_new()
395 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->pagepool), &chan->pagepool); in gf100_gr_chan_new()
399 ret = nvkm_memory_map(gr->pagepool, 0, chan->vmm, chan->pagepool, &args, sizeof(args)); in gf100_gr_chan_new()
404 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->bundle_cb), &chan->bundle_cb); in gf100_gr_chan_new()
408 ret = nvkm_memory_map(gr->bundle_cb, 0, chan->vmm, chan->bundle_cb, &args, sizeof(args)); in gf100_gr_chan_new()
413 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->attrib_cb), &chan->attrib_cb); in gf100_gr_chan_new()
417 if (device->card_type < GP100) { in gf100_gr_chan_new()
418 ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb, NULL, 0); in gf100_gr_chan_new()
422 ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb, in gf100_gr_chan_new()
429 if (gr->func->grctx->unknown_size) { in gf100_gr_chan_new()
430 ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->unknown), &chan->unknown); in gf100_gr_chan_new()
434 ret = nvkm_memory_map(gr->unknown, 0, chan->vmm, chan->unknown, in gf100_gr_chan_new()
441 mutex_lock(&gr->fecs.mutex); in gf100_gr_chan_new()
442 if (gr->data == NULL) { in gf100_gr_chan_new()
443 ret = gf100_grctx_generate(gr, chan, fifoch->inst); in gf100_gr_chan_new()
445 nvkm_error(&base->engine.subdev, "failed to construct context\n"); in gf100_gr_chan_new()
449 mutex_unlock(&gr->fecs.mutex); in gf100_gr_chan_new()
452 * fuc to modify some per-context register settings on first load in gf100_gr_chan_new()
455 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, in gf100_gr_chan_new()
456 false, &chan->mmio); in gf100_gr_chan_new()
460 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma); in gf100_gr_chan_new()
464 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm, in gf100_gr_chan_new()
465 chan->mmio_vma, &args, sizeof(args)); in gf100_gr_chan_new()
470 nvkm_kmap(chan->mmio); in gf100_gr_chan_new()
471 gr->func->grctx->pagepool(chan, chan->pagepool->addr); in gf100_gr_chan_new()
472 gr->func->grctx->bundle(chan, chan->bundle_cb->addr, gr->func->grctx->bundle_size); in gf100_gr_chan_new()
473 gr->func->grctx->attrib_cb(chan, chan->attrib_cb->addr, gr->func->grctx->attrib_cb_size(gr)); in gf100_gr_chan_new()
474 gr->func->grctx->attrib(chan); in gf100_gr_chan_new()
475 if (gr->func->grctx->patch_ltc) in gf100_gr_chan_new()
476 gr->func->grctx->patch_ltc(chan); in gf100_gr_chan_new()
477 if (gr->func->grctx->unknown_size) in gf100_gr_chan_new()
478 gr->func->grctx->unknown(chan, chan->unknown->addr, gr->func->grctx->unknown_size); in gf100_gr_chan_new()
479 nvkm_done(chan->mmio); in gf100_gr_chan_new()
480 return 0; in gf100_gr_chan_new()
489 { 0x400080, 1, 0x04, 0x003083c2 },
490 { 0x400088, 1, 0x04, 0x00006fe7 },
491 { 0x40008c, 1, 0x04, 0x00000000 },
492 { 0x400090, 1, 0x04, 0x00000030 },
493 { 0x40013c, 1, 0x04, 0x013901f7 },
494 { 0x400140, 1, 0x04, 0x00000100 },
495 { 0x400144, 1, 0x04, 0x00000000 },
496 { 0x400148, 1, 0x04, 0x00000110 },
497 { 0x400138, 1, 0x04, 0x00000000 },
498 { 0x400130, 2, 0x04, 0x00000000 },
499 { 0x400124, 1, 0x04, 0x00000002 },
505 { 0x40415c, 1, 0x04, 0x00000000 },
506 { 0x404170, 1, 0x04, 0x00000000 },
512 { 0x404488, 2, 0x04, 0x00000000 },
518 { 0x407808, 1, 0x04, 0x00000000 },
524 { 0x406024, 1, 0x04, 0x00000000 },
530 { 0x405844, 1, 0x04, 0x00ffffff },
531 { 0x405850, 1, 0x04, 0x00000000 },
532 { 0x405908, 1, 0x04, 0x00000000 },
538 { 0x40803c, 1, 0x04, 0x00000000 },
544 { 0x4184a0, 1, 0x04, 0x00000000 },
550 { 0x418604, 1, 0x04, 0x00000000 },
551 { 0x418680, 1, 0x04, 0x00000000 },
552 { 0x418714, 1, 0x04, 0x80000000 },
553 { 0x418384, 1, 0x04, 0x00000000 },
559 { 0x418814, 3, 0x04, 0x00000000 },
565 { 0x418b04, 1, 0x04, 0x00000000 },
571 { 0x4188c8, 1, 0x04, 0x80000000 },
572 { 0x4188cc, 1, 0x04, 0x00000000 },
573 { 0x4188d0, 1, 0x04, 0x00010000 },
574 { 0x4188d4, 1, 0x04, 0x00000001 },
580 { 0x418910, 1, 0x04, 0x00010001 },
581 { 0x418914, 1, 0x04, 0x00000301 },
582 { 0x418918, 1, 0x04, 0x00800000 },
583 { 0x418980, 1, 0x04, 0x77777770 },
584 { 0x418984, 3, 0x04, 0x77777777 },
590 { 0x418c04, 1, 0x04, 0x00000000 },
591 { 0x418c88, 1, 0x04, 0x00000000 },
597 { 0x418d00, 1, 0x04, 0x00000000 },
598 { 0x418f08, 1, 0x04, 0x00000000 },
599 { 0x418e00, 1, 0x04, 0x00000050 },
600 { 0x418e08, 1, 0x04, 0x00000000 },
606 { 0x41900c, 1, 0x04, 0x00000000 },
607 { 0x419018, 1, 0x04, 0x00000000 },
613 { 0x419d08, 2, 0x04, 0x00000000 },
614 { 0x419d10, 1, 0x04, 0x00000014 },
620 { 0x419ab0, 1, 0x04, 0x00000000 },
621 { 0x419ab8, 1, 0x04, 0x000000e7 },
622 { 0x419abc, 2, 0x04, 0x00000000 },
628 { 0x41980c, 3, 0x04, 0x00000000 },
629 { 0x419844, 1, 0x04, 0x00000000 },
630 { 0x41984c, 1, 0x04, 0x00005bc5 },
631 { 0x419850, 4, 0x04, 0x00000000 },
637 { 0x419c98, 1, 0x04, 0x00000000 },
638 { 0x419ca8, 1, 0x04, 0x80000000 },
639 { 0x419cb4, 1, 0x04, 0x00000000 },
640 { 0x419cb8, 1, 0x04, 0x00008bf4 },
641 { 0x419cbc, 1, 0x04, 0x28137606 },
642 { 0x419cc0, 2, 0x04, 0x00000000 },
648 { 0x419bd4, 1, 0x04, 0x00800000 },
649 { 0x419bdc, 1, 0x04, 0x00000000 },
655 { 0x419d2c, 1, 0x04, 0x00000000 },
661 { 0x419c0c, 1, 0x04, 0x00000000 },
667 { 0x419e00, 1, 0x04, 0x00000000 },
668 { 0x419ea0, 1, 0x04, 0x00000000 },
669 { 0x419ea4, 1, 0x04, 0x00000100 },
670 { 0x419ea8, 1, 0x04, 0x00001100 },
671 { 0x419eac, 1, 0x04, 0x11100702 },
672 { 0x419eb0, 1, 0x04, 0x00000003 },
673 { 0x419eb4, 4, 0x04, 0x00000000 },
674 { 0x419ec8, 1, 0x04, 0x06060618 },
675 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
676 { 0x419ed4, 1, 0x04, 0x011104f1 },
677 { 0x419edc, 1, 0x04, 0x00000000 },
678 { 0x419f00, 1, 0x04, 0x00000000 },
679 { 0x419f2c, 1, 0x04, 0x00000000 },
685 { 0x40880c, 1, 0x04, 0x00000000 },
686 { 0x408910, 9, 0x04, 0x00000000 },
687 { 0x408950, 1, 0x04, 0x00000000 },
688 { 0x408954, 1, 0x04, 0x0000ffff },
689 { 0x408984, 1, 0x04, 0x00000000 },
690 { 0x408988, 1, 0x04, 0x08040201 },
691 { 0x40898c, 1, 0x04, 0x80402010 },
697 { 0x4040f0, 1, 0x04, 0x00000000 },
703 { 0x419880, 1, 0x04, 0x00000002 },
746 return nvkm_rd32(gr->engine.subdev.device, 0x409b00); in gf100_gr_ctxsw_inst()
752 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_ctrl_ctxsw()
754 nvkm_wr32(device, 0x409804, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
755 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_ctrl_ctxsw()
756 nvkm_wr32(device, 0x409500, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
757 nvkm_wr32(device, 0x409504, mthd); in gf100_gr_fecs_ctrl_ctxsw()
759 u32 stat = nvkm_rd32(device, 0x409804); in gf100_gr_fecs_ctrl_ctxsw()
760 if (stat == 0x00000002) in gf100_gr_fecs_ctrl_ctxsw()
761 return -EIO; in gf100_gr_fecs_ctrl_ctxsw()
762 if (stat == 0x00000001) in gf100_gr_fecs_ctrl_ctxsw()
763 return 0; in gf100_gr_fecs_ctrl_ctxsw()
766 return -ETIMEDOUT; in gf100_gr_fecs_ctrl_ctxsw()
773 int ret = 0; in gf100_gr_fecs_start_ctxsw()
775 mutex_lock(&gr->fecs.mutex); in gf100_gr_fecs_start_ctxsw()
776 if (!--gr->fecs.disable) { in gf100_gr_fecs_start_ctxsw()
777 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x39))) in gf100_gr_fecs_start_ctxsw()
778 gr->fecs.disable++; in gf100_gr_fecs_start_ctxsw()
780 mutex_unlock(&gr->fecs.mutex); in gf100_gr_fecs_start_ctxsw()
788 int ret = 0; in gf100_gr_fecs_stop_ctxsw()
790 mutex_lock(&gr->fecs.mutex); in gf100_gr_fecs_stop_ctxsw()
791 if (!gr->fecs.disable++) { in gf100_gr_fecs_stop_ctxsw()
792 if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x38))) in gf100_gr_fecs_stop_ctxsw()
793 gr->fecs.disable--; in gf100_gr_fecs_stop_ctxsw()
795 mutex_unlock(&gr->fecs.mutex); in gf100_gr_fecs_stop_ctxsw()
802 int ret = 0; in gf100_gr_fecs_halt_pipeline()
804 if (gr->firmware) { in gf100_gr_fecs_halt_pipeline()
805 mutex_lock(&gr->fecs.mutex); in gf100_gr_fecs_halt_pipeline()
806 ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x04); in gf100_gr_fecs_halt_pipeline()
807 mutex_unlock(&gr->fecs.mutex); in gf100_gr_fecs_halt_pipeline()
816 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_wfi_golden_save()
818 nvkm_mask(device, 0x409800, 0x00000003, 0x00000000); in gf100_gr_fecs_wfi_golden_save()
819 nvkm_wr32(device, 0x409500, inst); in gf100_gr_fecs_wfi_golden_save()
820 nvkm_wr32(device, 0x409504, 0x00000009); in gf100_gr_fecs_wfi_golden_save()
822 u32 stat = nvkm_rd32(device, 0x409800); in gf100_gr_fecs_wfi_golden_save()
823 if (stat & 0x00000002) in gf100_gr_fecs_wfi_golden_save()
824 return -EIO; in gf100_gr_fecs_wfi_golden_save()
825 if (stat & 0x00000001) in gf100_gr_fecs_wfi_golden_save()
826 return 0; in gf100_gr_fecs_wfi_golden_save()
829 return -ETIMEDOUT; in gf100_gr_fecs_wfi_golden_save()
835 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_bind_pointer()
837 nvkm_mask(device, 0x409800, 0x00000030, 0x00000000); in gf100_gr_fecs_bind_pointer()
838 nvkm_wr32(device, 0x409500, inst); in gf100_gr_fecs_bind_pointer()
839 nvkm_wr32(device, 0x409504, 0x00000003); in gf100_gr_fecs_bind_pointer()
841 u32 stat = nvkm_rd32(device, 0x409800); in gf100_gr_fecs_bind_pointer()
842 if (stat & 0x00000020) in gf100_gr_fecs_bind_pointer()
843 return -EIO; in gf100_gr_fecs_bind_pointer()
844 if (stat & 0x00000010) in gf100_gr_fecs_bind_pointer()
845 return 0; in gf100_gr_fecs_bind_pointer()
848 return -ETIMEDOUT; in gf100_gr_fecs_bind_pointer()
854 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_set_reglist_virtual_address()
856 nvkm_wr32(device, 0x409810, addr >> 8); in gf100_gr_fecs_set_reglist_virtual_address()
857 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_reglist_virtual_address()
858 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_set_reglist_virtual_address()
859 nvkm_wr32(device, 0x409504, 0x00000032); in gf100_gr_fecs_set_reglist_virtual_address()
861 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_virtual_address()
862 return 0; in gf100_gr_fecs_set_reglist_virtual_address()
865 return -ETIMEDOUT; in gf100_gr_fecs_set_reglist_virtual_address()
871 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_set_reglist_bind_instance()
873 nvkm_wr32(device, 0x409810, inst); in gf100_gr_fecs_set_reglist_bind_instance()
874 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_reglist_bind_instance()
875 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_set_reglist_bind_instance()
876 nvkm_wr32(device, 0x409504, 0x00000031); in gf100_gr_fecs_set_reglist_bind_instance()
878 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_bind_instance()
879 return 0; in gf100_gr_fecs_set_reglist_bind_instance()
882 return -ETIMEDOUT; in gf100_gr_fecs_set_reglist_bind_instance()
888 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_reglist_image_size()
890 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_reglist_image_size()
891 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_discover_reglist_image_size()
892 nvkm_wr32(device, 0x409504, 0x00000030); in gf100_gr_fecs_discover_reglist_image_size()
894 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_reglist_image_size()
895 return 0; in gf100_gr_fecs_discover_reglist_image_size()
898 return -ETIMEDOUT; in gf100_gr_fecs_discover_reglist_image_size()
916 ret = gf100_gr_fecs_set_reglist_bind_instance(gr, 0); in gf100_gr_fecs_elpg_bind()
920 return gf100_gr_fecs_set_reglist_virtual_address(gr, 0); in gf100_gr_fecs_elpg_bind()
926 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_pm_image_size()
928 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_pm_image_size()
929 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_pm_image_size()
930 nvkm_wr32(device, 0x409504, 0x00000025); in gf100_gr_fecs_discover_pm_image_size()
932 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_pm_image_size()
933 return 0; in gf100_gr_fecs_discover_pm_image_size()
936 return -ETIMEDOUT; in gf100_gr_fecs_discover_pm_image_size()
942 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_zcull_image_size()
944 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_zcull_image_size()
945 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_zcull_image_size()
946 nvkm_wr32(device, 0x409504, 0x00000016); in gf100_gr_fecs_discover_zcull_image_size()
948 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_zcull_image_size()
949 return 0; in gf100_gr_fecs_discover_zcull_image_size()
952 return -ETIMEDOUT; in gf100_gr_fecs_discover_zcull_image_size()
958 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_image_size()
960 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_image_size()
961 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_image_size()
962 nvkm_wr32(device, 0x409504, 0x00000010); in gf100_gr_fecs_discover_image_size()
964 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_image_size()
965 return 0; in gf100_gr_fecs_discover_image_size()
968 return -ETIMEDOUT; in gf100_gr_fecs_discover_image_size()
974 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_set_watchdog_timeout()
976 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_watchdog_timeout()
977 nvkm_wr32(device, 0x409500, timeout); in gf100_gr_fecs_set_watchdog_timeout()
978 nvkm_wr32(device, 0x409504, 0x00000021); in gf100_gr_fecs_set_watchdog_timeout()
985 if (!gr->firmware) { in gf100_gr_chsw_load()
986 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); in gf100_gr_chsw_load()
987 if (trace & 0x00000040) in gf100_gr_chsw_load()
990 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); in gf100_gr_chsw_load()
991 if (mthd & 0x00080000) in gf100_gr_chsw_load()
1000 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_rops()
1001 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; in gf100_gr_rops()
1007 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, in gf100_gr_zbc_init()
1008 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; in gf100_gr_zbc_init()
1009 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, in gf100_gr_zbc_init()
1010 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; in gf100_gr_zbc_init()
1011 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, in gf100_gr_zbc_init()
1012 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; in gf100_gr_zbc_init()
1013 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, in gf100_gr_zbc_init()
1014 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; in gf100_gr_zbc_init()
1015 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_init()
1016 int index, c = ltc->zbc_color_min, d = ltc->zbc_depth_min, s = ltc->zbc_depth_min; in gf100_gr_zbc_init()
1018 if (!gr->zbc_color[0].format) { in gf100_gr_zbc_init()
1019 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++; in gf100_gr_zbc_init()
1020 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++; in gf100_gr_zbc_init()
1021 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++; in gf100_gr_zbc_init()
1022 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++; in gf100_gr_zbc_init()
1023 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++; in gf100_gr_zbc_init()
1024 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++; in gf100_gr_zbc_init()
1025 if (gr->func->zbc->stencil_get) { in gf100_gr_zbc_init()
1026 gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++; in gf100_gr_zbc_init()
1027 gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++; in gf100_gr_zbc_init()
1028 gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++; in gf100_gr_zbc_init()
1032 for (index = c; index <= ltc->zbc_color_max; index++) in gf100_gr_zbc_init()
1033 gr->func->zbc->clear_color(gr, index); in gf100_gr_zbc_init()
1034 for (index = d; index <= ltc->zbc_depth_max; index++) in gf100_gr_zbc_init()
1035 gr->func->zbc->clear_depth(gr, index); in gf100_gr_zbc_init()
1037 if (gr->func->zbc->clear_stencil) { in gf100_gr_zbc_init()
1038 for (index = s; index <= ltc->zbc_depth_max; index++) in gf100_gr_zbc_init()
1039 gr->func->zbc->clear_stencil(gr, index); in gf100_gr_zbc_init()
1045 * MC (0x200) register, or GR is not busy and a context switch is not in
1051 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_wait_idle()
1052 struct nvkm_device *device = subdev->device; in gf100_gr_wait_idle()
1058 * required to make sure FIFO_ENGINE_STATUS (0x2640) is in gf100_gr_wait_idle()
1059 * up-to-date in gf100_gr_wait_idle()
1061 nvkm_rd32(device, 0x400700); in gf100_gr_wait_idle()
1063 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; in gf100_gr_wait_idle()
1064 ctxsw_active = nvkm_fifo_ctxsw_in_progress(&gr->base.engine); in gf100_gr_wait_idle()
1065 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; in gf100_gr_wait_idle()
1068 return 0; in gf100_gr_wait_idle()
1074 return -EAGAIN; in gf100_gr_wait_idle()
1080 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_mmio()
1085 u32 next = init->addr + init->count * init->pitch; in gf100_gr_mmio()
1086 u32 addr = init->addr; in gf100_gr_mmio()
1088 nvkm_wr32(device, addr, init->data); in gf100_gr_mmio()
1089 addr += init->pitch; in gf100_gr_mmio()
1097 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_icmd()
1100 u64 data = 0; in gf100_gr_icmd()
1102 nvkm_wr32(device, 0x400208, 0x80000000); in gf100_gr_icmd()
1105 u32 next = init->addr + init->count * init->pitch; in gf100_gr_icmd()
1106 u32 addr = init->addr; in gf100_gr_icmd()
1108 if ((pack == p && init == p->init) || data != init->data) { in gf100_gr_icmd()
1109 nvkm_wr32(device, 0x400204, init->data); in gf100_gr_icmd()
1110 if (pack->type == 64) in gf100_gr_icmd()
1111 nvkm_wr32(device, 0x40020c, upper_32_bits(init->data)); in gf100_gr_icmd()
1112 data = init->data; in gf100_gr_icmd()
1116 nvkm_wr32(device, 0x400200, addr); in gf100_gr_icmd()
1121 if ((addr & 0xffff) == 0xe100) in gf100_gr_icmd()
1124 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) in gf100_gr_icmd()
1127 addr += init->pitch; in gf100_gr_icmd()
1131 nvkm_wr32(device, 0x400208, 0x00000000); in gf100_gr_icmd()
1137 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_mthd()
1140 u32 data = 0; in gf100_gr_mthd()
1143 u32 ctrl = 0x80000000 | pack->type; in gf100_gr_mthd()
1144 u32 next = init->addr + init->count * init->pitch; in gf100_gr_mthd()
1145 u32 addr = init->addr; in gf100_gr_mthd()
1147 if ((pack == p && init == p->init) || data != init->data) { in gf100_gr_mthd()
1148 nvkm_wr32(device, 0x40448c, init->data); in gf100_gr_mthd()
1149 data = init->data; in gf100_gr_mthd()
1153 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); in gf100_gr_mthd()
1154 addr += init->pitch; in gf100_gr_mthd()
1165 cfg = (u32)gr->gpc_nr; in gf100_gr_units()
1166 cfg |= (u32)gr->tpc_total << 8; in gf100_gr_units()
1167 cfg |= (u64)gr->rop_nr << 32; in gf100_gr_units()
1173 { 0x00000001, "INJECTED_BUNDLE_ERROR" },
1174 { 0x00000002, "CLASS_SUBCH_MISMATCH" },
1175 { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
1180 { 0x00000001, "PUSH_TOO_MUCH_DATA" },
1181 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
1186 { 0x00000001, "TEMP_TOO_SMALL" },
1191 { 0x00000001, "INTR" },
1192 { 0x00000002, "LDCONST_OOB" },
1197 { 0x00000001, "TOO_FEW_PARAMS" },
1198 { 0x00000002, "TOO_MANY_PARAMS" },
1199 { 0x00000004, "ILLEGAL_OPCODE" },
1200 { 0x00000008, "DOUBLE_BRANCH" },
1201 { 0x00000010, "WATCHDOG" },
1206 { 0x00000040, "CTA_RESUME" },
1207 { 0x00000080, "CONSTANT_BUFFER_SIZE" },
1208 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
1209 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
1210 { 0x00000800, "WARP_CSTACK_SIZE" },
1211 { 0x00001000, "TOTAL_TEMP_SIZE" },
1212 { 0x00002000, "REGISTER_COUNT" },
1213 { 0x00040000, "TOTAL_THREADS" },
1214 { 0x00100000, "PROGRAM_OFFSET" },
1215 { 0x00200000, "SHARED_MEMORY_SIZE" },
1216 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
1217 { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
1218 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
1219 { 0x04000000, "TOTAL_REGISTER_COUNT" },
1224 { 0x00000002, "RT_PITCH_OVERRUN" },
1225 { 0x00000010, "RT_WIDTH_OVERRUN" },
1226 { 0x00000020, "RT_HEIGHT_OVERRUN" },
1227 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
1228 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
1229 { 0x00000400, "RT_LINEAR_MISMATCH" },
1236 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_trap_gpc_rop()
1237 struct nvkm_device *device = subdev->device; in gf100_gr_trap_gpc_rop()
1241 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; in gf100_gr_trap_gpc_rop()
1242 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
1243 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
1244 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
1246 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); in gf100_gr_trap_gpc_rop()
1250 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, in gf100_gr_trap_gpc_rop()
1251 (trap[2] >> 8) & 0x3f, trap[3] & 0xff); in gf100_gr_trap_gpc_rop()
1252 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
1256 { 0x01, "STACK_ERROR" },
1257 { 0x02, "API_STACK_ERROR" },
1258 { 0x03, "RET_EMPTY_STACK_ERROR" },
1259 { 0x04, "PC_WRAP" },
1260 { 0x05, "MISALIGNED_PC" },
1261 { 0x06, "PC_OVERFLOW" },
1262 { 0x07, "MISALIGNED_IMMC_ADDR" },
1263 { 0x08, "MISALIGNED_REG" },
1264 { 0x09, "ILLEGAL_INSTR_ENCODING" },
1265 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
1266 { 0x0b, "ILLEGAL_INSTR_PARAM" },
1267 { 0x0c, "INVALID_CONST_ADDR" },
1268 { 0x0d, "OOR_REG" },
1269 { 0x0e, "OOR_ADDR" },
1270 { 0x0f, "MISALIGNED_ADDR" },
1271 { 0x10, "INVALID_ADDR_SPACE" },
1272 { 0x11, "ILLEGAL_INSTR_PARAM2" },
1273 { 0x12, "INVALID_CONST_ADDR_LDC" },
1274 { 0x13, "GEOMETRY_SM_ERROR" },
1275 { 0x14, "DIVERGENT" },
1276 { 0x15, "WARP_EXIT" },
1281 { 0x00000001, "SM_TO_SM_FAULT" },
1282 { 0x00000002, "L1_ERROR" },
1283 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
1284 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1285 { 0x00000010, "BPT_INT" },
1286 { 0x00000020, "BPT_PAUSE" },
1287 { 0x00000040, "SINGLE_STEP_COMPLETE" },
1288 { 0x20000000, "ECC_SEC_ERROR" },
1289 { 0x40000000, "ECC_DED_ERROR" },
1290 { 0x80000000, "TIMEOUT" },
1297 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_trap_mp()
1298 struct nvkm_device *device = subdev->device; in gf100_gr_trap_mp()
1299 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
1300 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
1305 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); in gf100_gr_trap_mp()
1309 gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); in gf100_gr_trap_mp()
1311 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); in gf100_gr_trap_mp()
1312 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); in gf100_gr_trap_mp()
1318 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_trap_tpc()
1319 struct nvkm_device *device = subdev->device; in gf100_gr_trap_tpc()
1320 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); in gf100_gr_trap_tpc()
1322 if (stat & 0x00000001) { in gf100_gr_trap_tpc()
1323 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); in gf100_gr_trap_tpc()
1325 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); in gf100_gr_trap_tpc()
1326 stat &= ~0x00000001; in gf100_gr_trap_tpc()
1329 if (stat & 0x00000002) { in gf100_gr_trap_tpc()
1330 gr->func->trap_mp(gr, gpc, tpc); in gf100_gr_trap_tpc()
1331 stat &= ~0x00000002; in gf100_gr_trap_tpc()
1334 if (stat & 0x00000004) { in gf100_gr_trap_tpc()
1335 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); in gf100_gr_trap_tpc()
1337 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); in gf100_gr_trap_tpc()
1338 stat &= ~0x00000004; in gf100_gr_trap_tpc()
1341 if (stat & 0x00000008) { in gf100_gr_trap_tpc()
1342 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); in gf100_gr_trap_tpc()
1344 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); in gf100_gr_trap_tpc()
1345 stat &= ~0x00000008; in gf100_gr_trap_tpc()
1348 if (stat & 0x00000010) { in gf100_gr_trap_tpc()
1349 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); in gf100_gr_trap_tpc()
1351 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000); in gf100_gr_trap_tpc()
1352 stat &= ~0x00000010; in gf100_gr_trap_tpc()
1363 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_trap_gpc()
1364 struct nvkm_device *device = subdev->device; in gf100_gr_trap_gpc()
1365 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); in gf100_gr_trap_gpc()
1368 if (stat & 0x00000001) { in gf100_gr_trap_gpc()
1370 stat &= ~0x00000001; in gf100_gr_trap_gpc()
1373 if (stat & 0x00000002) { in gf100_gr_trap_gpc()
1374 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); in gf100_gr_trap_gpc()
1376 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_trap_gpc()
1377 stat &= ~0x00000002; in gf100_gr_trap_gpc()
1380 if (stat & 0x00000004) { in gf100_gr_trap_gpc()
1381 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); in gf100_gr_trap_gpc()
1383 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_trap_gpc()
1384 stat &= ~0x00000004; in gf100_gr_trap_gpc()
1387 if (stat & 0x00000008) { in gf100_gr_trap_gpc()
1388 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); in gf100_gr_trap_gpc()
1390 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_trap_gpc()
1391 stat &= ~0x00000009; in gf100_gr_trap_gpc()
1394 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_gr_trap_gpc()
1395 u32 mask = 0x00010000 << tpc; in gf100_gr_trap_gpc()
1398 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); in gf100_gr_trap_gpc()
1411 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_trap_intr()
1412 struct nvkm_device *device = subdev->device; in gf100_gr_trap_intr()
1414 u32 trap = nvkm_rd32(device, 0x400108); in gf100_gr_trap_intr()
1417 if (trap & 0x00000001) { in gf100_gr_trap_intr()
1418 u32 stat = nvkm_rd32(device, 0x404000); in gf100_gr_trap_intr()
1421 stat & 0x3fffffff); in gf100_gr_trap_intr()
1423 nvkm_wr32(device, 0x404000, 0xc0000000); in gf100_gr_trap_intr()
1424 nvkm_wr32(device, 0x400108, 0x00000001); in gf100_gr_trap_intr()
1425 trap &= ~0x00000001; in gf100_gr_trap_intr()
1428 if (trap & 0x00000002) { in gf100_gr_trap_intr()
1429 u32 stat = nvkm_rd32(device, 0x404600); in gf100_gr_trap_intr()
1432 stat & 0x3fffffff); in gf100_gr_trap_intr()
1435 nvkm_wr32(device, 0x404600, 0xc0000000); in gf100_gr_trap_intr()
1436 nvkm_wr32(device, 0x400108, 0x00000002); in gf100_gr_trap_intr()
1437 trap &= ~0x00000002; in gf100_gr_trap_intr()
1440 if (trap & 0x00000008) { in gf100_gr_trap_intr()
1441 u32 stat = nvkm_rd32(device, 0x408030); in gf100_gr_trap_intr()
1444 stat & 0x3fffffff); in gf100_gr_trap_intr()
1446 nvkm_wr32(device, 0x408030, 0xc0000000); in gf100_gr_trap_intr()
1447 nvkm_wr32(device, 0x400108, 0x00000008); in gf100_gr_trap_intr()
1448 trap &= ~0x00000008; in gf100_gr_trap_intr()
1451 if (trap & 0x00000010) { in gf100_gr_trap_intr()
1452 u32 stat = nvkm_rd32(device, 0x405840); in gf100_gr_trap_intr()
1453 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", in gf100_gr_trap_intr()
1454 stat, stat & 0xffffff, (stat >> 24) & 0x3f); in gf100_gr_trap_intr()
1455 nvkm_wr32(device, 0x405840, 0xc0000000); in gf100_gr_trap_intr()
1456 nvkm_wr32(device, 0x400108, 0x00000010); in gf100_gr_trap_intr()
1457 trap &= ~0x00000010; in gf100_gr_trap_intr()
1460 if (trap & 0x00000040) { in gf100_gr_trap_intr()
1461 u32 stat = nvkm_rd32(device, 0x40601c); in gf100_gr_trap_intr()
1464 stat & 0x3fffffff); in gf100_gr_trap_intr()
1467 nvkm_wr32(device, 0x40601c, 0xc0000000); in gf100_gr_trap_intr()
1468 nvkm_wr32(device, 0x400108, 0x00000040); in gf100_gr_trap_intr()
1469 trap &= ~0x00000040; in gf100_gr_trap_intr()
1472 if (trap & 0x00000080) { in gf100_gr_trap_intr()
1473 u32 stat = nvkm_rd32(device, 0x404490); in gf100_gr_trap_intr()
1474 u32 pc = nvkm_rd32(device, 0x404494); in gf100_gr_trap_intr()
1475 u32 op = nvkm_rd32(device, 0x40449c); in gf100_gr_trap_intr()
1478 stat & 0x1fffffff); in gf100_gr_trap_intr()
1479 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", in gf100_gr_trap_intr()
1480 stat, error, pc & 0x7ff, in gf100_gr_trap_intr()
1481 (pc & 0x10000000) ? "" : " (invalid)", in gf100_gr_trap_intr()
1484 nvkm_wr32(device, 0x404490, 0xc0000000); in gf100_gr_trap_intr()
1485 nvkm_wr32(device, 0x400108, 0x00000080); in gf100_gr_trap_intr()
1486 trap &= ~0x00000080; in gf100_gr_trap_intr()
1489 if (trap & 0x00000100) { in gf100_gr_trap_intr()
1490 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; in gf100_gr_trap_intr()
1496 nvkm_wr32(device, 0x407020, 0x40000000); in gf100_gr_trap_intr()
1497 nvkm_wr32(device, 0x400108, 0x00000100); in gf100_gr_trap_intr()
1498 trap &= ~0x00000100; in gf100_gr_trap_intr()
1501 if (trap & 0x01000000) { in gf100_gr_trap_intr()
1502 u32 stat = nvkm_rd32(device, 0x400118); in gf100_gr_trap_intr()
1503 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { in gf100_gr_trap_intr()
1504 u32 mask = 0x00000001 << gpc; in gf100_gr_trap_intr()
1507 nvkm_wr32(device, 0x400118, mask); in gf100_gr_trap_intr()
1511 nvkm_wr32(device, 0x400108, 0x01000000); in gf100_gr_trap_intr()
1512 trap &= ~0x01000000; in gf100_gr_trap_intr()
1515 if (trap & 0x02000000) { in gf100_gr_trap_intr()
1516 for (rop = 0; rop < gr->rop_nr; rop++) { in gf100_gr_trap_intr()
1517 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); in gf100_gr_trap_intr()
1518 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); in gf100_gr_trap_intr()
1521 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); in gf100_gr_trap_intr()
1522 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); in gf100_gr_trap_intr()
1524 nvkm_wr32(device, 0x400108, 0x02000000); in gf100_gr_trap_intr()
1525 trap &= ~0x02000000; in gf100_gr_trap_intr()
1530 nvkm_wr32(device, 0x400108, trap); in gf100_gr_trap_intr()
1537 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_ctxctl_debug_unit()
1538 struct nvkm_device *device = subdev->device; in gf100_gr_ctxctl_debug_unit()
1539 nvkm_error(subdev, "%06x - done %08x\n", base, in gf100_gr_ctxctl_debug_unit()
1540 nvkm_rd32(device, base + 0x400)); in gf100_gr_ctxctl_debug_unit()
1541 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, in gf100_gr_ctxctl_debug_unit()
1542 nvkm_rd32(device, base + 0x800), in gf100_gr_ctxctl_debug_unit()
1543 nvkm_rd32(device, base + 0x804), in gf100_gr_ctxctl_debug_unit()
1544 nvkm_rd32(device, base + 0x808), in gf100_gr_ctxctl_debug_unit()
1545 nvkm_rd32(device, base + 0x80c)); in gf100_gr_ctxctl_debug_unit()
1546 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, in gf100_gr_ctxctl_debug_unit()
1547 nvkm_rd32(device, base + 0x810), in gf100_gr_ctxctl_debug_unit()
1548 nvkm_rd32(device, base + 0x814), in gf100_gr_ctxctl_debug_unit()
1549 nvkm_rd32(device, base + 0x818), in gf100_gr_ctxctl_debug_unit()
1550 nvkm_rd32(device, base + 0x81c)); in gf100_gr_ctxctl_debug_unit()
1556 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_ctxctl_debug()
1557 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; in gf100_gr_ctxctl_debug()
1560 gf100_gr_ctxctl_debug_unit(gr, 0x409000); in gf100_gr_ctxctl_debug()
1561 for (gpc = 0; gpc < gpcnr; gpc++) in gf100_gr_ctxctl_debug()
1562 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); in gf100_gr_ctxctl_debug()
1568 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_ctxctl_isr()
1569 struct nvkm_device *device = subdev->device; in gf100_gr_ctxctl_isr()
1570 u32 stat = nvkm_rd32(device, 0x409c18); in gf100_gr_ctxctl_isr()
1572 if (!gr->firmware && (stat & 0x00000001)) { in gf100_gr_ctxctl_isr()
1573 u32 code = nvkm_rd32(device, 0x409814); in gf100_gr_ctxctl_isr()
1575 u32 class = nvkm_rd32(device, 0x409808); in gf100_gr_ctxctl_isr()
1576 u32 addr = nvkm_rd32(device, 0x40980c); in gf100_gr_ctxctl_isr()
1577 u32 subc = (addr & 0x00070000) >> 16; in gf100_gr_ctxctl_isr()
1578 u32 mthd = (addr & 0x00003ffc); in gf100_gr_ctxctl_isr()
1579 u32 data = nvkm_rd32(device, 0x409810); in gf100_gr_ctxctl_isr()
1587 nvkm_wr32(device, 0x409c20, 0x00000001); in gf100_gr_ctxctl_isr()
1588 stat &= ~0x00000001; in gf100_gr_ctxctl_isr()
1591 if (!gr->firmware && (stat & 0x00080000)) { in gf100_gr_ctxctl_isr()
1594 nvkm_wr32(device, 0x409c20, 0x00080000); in gf100_gr_ctxctl_isr()
1595 stat &= ~0x00080000; in gf100_gr_ctxctl_isr()
1601 nvkm_wr32(device, 0x409c20, stat); in gf100_gr_ctxctl_isr()
1609 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_intr()
1610 struct nvkm_device *device = subdev->device; in gf100_gr_intr()
1613 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; in gf100_gr_intr()
1614 u32 stat = nvkm_rd32(device, 0x400100); in gf100_gr_intr()
1615 u32 addr = nvkm_rd32(device, 0x400704); in gf100_gr_intr()
1616 u32 mthd = (addr & 0x00003ffc); in gf100_gr_intr()
1617 u32 subc = (addr & 0x00070000) >> 16; in gf100_gr_intr()
1618 u32 data = nvkm_rd32(device, 0x400708); in gf100_gr_intr()
1619 u32 code = nvkm_rd32(device, 0x400110); in gf100_gr_intr()
1622 int chid = -1; in gf100_gr_intr()
1624 chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags); in gf100_gr_intr()
1626 name = chan->name; in gf100_gr_intr()
1627 chid = chan->id; in gf100_gr_intr()
1630 if (device->card_type < NV_E0 || subc < 4) in gf100_gr_intr()
1631 class = nvkm_rd32(device, 0x404200 + (subc * 4)); in gf100_gr_intr()
1633 class = 0x0000; in gf100_gr_intr()
1635 if (stat & 0x00000001) { in gf100_gr_intr()
1640 nvkm_wr32(device, 0x400100, 0x00000001); in gf100_gr_intr()
1641 stat &= ~0x00000001; in gf100_gr_intr()
1644 if (stat & 0x00000010) { in gf100_gr_intr()
1651 nvkm_wr32(device, 0x400100, 0x00000010); in gf100_gr_intr()
1652 stat &= ~0x00000010; in gf100_gr_intr()
1655 if (stat & 0x00000020) { in gf100_gr_intr()
1659 nvkm_wr32(device, 0x400100, 0x00000020); in gf100_gr_intr()
1660 stat &= ~0x00000020; in gf100_gr_intr()
1663 if (stat & 0x00100000) { in gf100_gr_intr()
1668 code, en ? en->name : "", chid, inst << 12, in gf100_gr_intr()
1670 nvkm_wr32(device, 0x400100, 0x00100000); in gf100_gr_intr()
1671 stat &= ~0x00100000; in gf100_gr_intr()
1674 if (stat & 0x00200000) { in gf100_gr_intr()
1678 nvkm_wr32(device, 0x400100, 0x00200000); in gf100_gr_intr()
1679 stat &= ~0x00200000; in gf100_gr_intr()
1682 if (stat & 0x00080000) { in gf100_gr_intr()
1684 nvkm_wr32(device, 0x400100, 0x00080000); in gf100_gr_intr()
1685 stat &= ~0x00080000; in gf100_gr_intr()
1690 nvkm_wr32(device, 0x400100, stat); in gf100_gr_intr()
1693 nvkm_wr32(device, 0x400500, 0x00010001); in gf100_gr_intr()
1702 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); in gf100_gr_init_fw()
1703 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); in gf100_gr_init_fw()
1711 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_csdata()
1714 u32 addr = ~0, prev = ~0, xfer = 0; in gf100_gr_init_csdata()
1717 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); in gf100_gr_init_csdata()
1718 star = nvkm_rd32(device, falcon + 0x01c4); in gf100_gr_init_csdata()
1719 temp = nvkm_rd32(device, falcon + 0x01c4); in gf100_gr_init_csdata()
1722 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); in gf100_gr_init_csdata()
1725 u32 head = init->addr - base; in gf100_gr_init_csdata()
1726 u32 tail = head + init->count * init->pitch; in gf100_gr_init_csdata()
1730 u32 data = ((--xfer << 26) | addr); in gf100_gr_init_csdata()
1731 nvkm_wr32(device, falcon + 0x01c4, data); in gf100_gr_init_csdata()
1735 xfer = 0; in gf100_gr_init_csdata()
1739 head = head + init->pitch; in gf100_gr_init_csdata()
1743 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); in gf100_gr_init_csdata()
1744 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); in gf100_gr_init_csdata()
1745 nvkm_wr32(device, falcon + 0x01c4, star + 4); in gf100_gr_init_csdata()
1752 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_init_ctxctl_ext()
1753 struct nvkm_device *device = subdev->device; in gf100_gr_init_ctxctl_ext()
1754 u32 lsf_mask = 0; in gf100_gr_init_ctxctl_ext()
1758 nvkm_mc_unk260(device, 0); in gf100_gr_init_ctxctl_ext()
1760 /* securely-managed falcons must be reset using secure boot */ in gf100_gr_init_ctxctl_ext()
1763 gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst, in gf100_gr_init_ctxctl_ext()
1764 &gr->fecs.data); in gf100_gr_init_ctxctl_ext()
1770 gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst, in gf100_gr_init_ctxctl_ext()
1771 &gr->gpccs.data); in gf100_gr_init_ctxctl_ext()
1785 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_init_ctxctl_ext()
1786 nvkm_wr32(device, 0x41a10c, 0x00000000); in gf100_gr_init_ctxctl_ext()
1787 nvkm_wr32(device, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl_ext()
1789 nvkm_falcon_start(&gr->gpccs.falcon); in gf100_gr_init_ctxctl_ext()
1790 nvkm_falcon_start(&gr->fecs.falcon); in gf100_gr_init_ctxctl_ext()
1793 if (nvkm_rd32(device, 0x409800) & 0x00000001) in gf100_gr_init_ctxctl_ext()
1795 ) < 0) in gf100_gr_init_ctxctl_ext()
1796 return -EBUSY; in gf100_gr_init_ctxctl_ext()
1798 gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff); in gf100_gr_init_ctxctl_ext()
1801 ret = gf100_gr_fecs_discover_image_size(gr, &gr->size); in gf100_gr_init_ctxctl_ext()
1806 ret = gf100_gr_fecs_discover_zcull_image_size(gr, &gr->size_zcull); in gf100_gr_init_ctxctl_ext()
1811 ret = gf100_gr_fecs_discover_pm_image_size(gr, &gr->size_pm); in gf100_gr_init_ctxctl_ext()
1821 if (0) { in gf100_gr_init_ctxctl_ext()
1827 return 0; in gf100_gr_init_ctxctl_ext()
1833 const struct gf100_grctx_func *grctx = gr->func->grctx; in gf100_gr_init_ctxctl_int()
1834 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_init_ctxctl_int()
1835 struct nvkm_device *device = subdev->device; in gf100_gr_init_ctxctl_int()
1837 if (!gr->func->fecs.ucode) { in gf100_gr_init_ctxctl_int()
1838 return -ENOSYS; in gf100_gr_init_ctxctl_int()
1842 nvkm_mc_unk260(device, 0); in gf100_gr_init_ctxctl_int()
1843 nvkm_falcon_load_dmem(&gr->fecs.falcon, in gf100_gr_init_ctxctl_int()
1844 gr->func->fecs.ucode->data.data, 0x0, in gf100_gr_init_ctxctl_int()
1845 gr->func->fecs.ucode->data.size, 0); in gf100_gr_init_ctxctl_int()
1846 nvkm_falcon_load_imem(&gr->fecs.falcon, in gf100_gr_init_ctxctl_int()
1847 gr->func->fecs.ucode->code.data, 0x0, in gf100_gr_init_ctxctl_int()
1848 gr->func->fecs.ucode->code.size, 0, 0, false); in gf100_gr_init_ctxctl_int()
1851 nvkm_falcon_load_dmem(&gr->gpccs.falcon, in gf100_gr_init_ctxctl_int()
1852 gr->func->gpccs.ucode->data.data, 0x0, in gf100_gr_init_ctxctl_int()
1853 gr->func->gpccs.ucode->data.size, 0); in gf100_gr_init_ctxctl_int()
1854 nvkm_falcon_load_imem(&gr->gpccs.falcon, in gf100_gr_init_ctxctl_int()
1855 gr->func->gpccs.ucode->code.data, 0x0, in gf100_gr_init_ctxctl_int()
1856 gr->func->gpccs.ucode->code.size, 0, 0, false); in gf100_gr_init_ctxctl_int()
1860 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); in gf100_gr_init_ctxctl_int()
1861 gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000); in gf100_gr_init_ctxctl_int()
1862 gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000); in gf100_gr_init_ctxctl_int()
1863 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); in gf100_gr_init_ctxctl_int()
1864 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); in gf100_gr_init_ctxctl_int()
1867 nvkm_wr32(device, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl_int()
1868 nvkm_wr32(device, 0x409100, 0x00000002); in gf100_gr_init_ctxctl_int()
1870 if (nvkm_rd32(device, 0x409800) & 0x80000000) in gf100_gr_init_ctxctl_int()
1872 ) < 0) { in gf100_gr_init_ctxctl_int()
1874 return -EBUSY; in gf100_gr_init_ctxctl_int()
1877 gr->size = nvkm_rd32(device, 0x409804); in gf100_gr_init_ctxctl_int()
1878 return 0; in gf100_gr_init_ctxctl_int()
1886 if (gr->firmware) in gf100_gr_init_ctxctl()
1899 for (tpc = 0; tpc < gr->tpc_max; tpc++) { in gf100_gr_oneinit_sm_id()
1900 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_oneinit_sm_id()
1901 if (tpc < gr->tpc_nr[gpc]) { in gf100_gr_oneinit_sm_id()
1902 gr->sm[gr->sm_nr].gpc = gpc; in gf100_gr_oneinit_sm_id()
1903 gr->sm[gr->sm_nr].tpc = tpc; in gf100_gr_oneinit_sm_id()
1904 gr->sm_nr++; in gf100_gr_oneinit_sm_id()
1909 return 0; in gf100_gr_oneinit_sm_id()
1923 switch (gr->tpc_total) { in gf100_gr_oneinit_tiles()
1924 case 15: gr->screen_tile_row_offset = 0x06; break; in gf100_gr_oneinit_tiles()
1925 case 14: gr->screen_tile_row_offset = 0x05; break; in gf100_gr_oneinit_tiles()
1926 case 13: gr->screen_tile_row_offset = 0x02; break; in gf100_gr_oneinit_tiles()
1927 case 11: gr->screen_tile_row_offset = 0x07; break; in gf100_gr_oneinit_tiles()
1928 case 10: gr->screen_tile_row_offset = 0x06; break; in gf100_gr_oneinit_tiles()
1930 case 5: gr->screen_tile_row_offset = 0x01; break; in gf100_gr_oneinit_tiles()
1931 case 3: gr->screen_tile_row_offset = 0x02; break; in gf100_gr_oneinit_tiles()
1933 case 1: gr->screen_tile_row_offset = 0x01; break; in gf100_gr_oneinit_tiles()
1934 default: gr->screen_tile_row_offset = 0x03; in gf100_gr_oneinit_tiles()
1935 for (i = 0; i < ARRAY_SIZE(primes); i++) { in gf100_gr_oneinit_tiles()
1936 if (gr->tpc_total % primes[i]) { in gf100_gr_oneinit_tiles()
1937 gr->screen_tile_row_offset = primes[i]; in gf100_gr_oneinit_tiles()
1944 /* Sort GPCs by TPC count, highest-to-lowest. */ in gf100_gr_oneinit_tiles()
1945 for (i = 0; i < gr->gpc_nr; i++) in gf100_gr_oneinit_tiles()
1950 for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) { in gf100_gr_oneinit_tiles()
1951 if (gr->tpc_nr[gpc_map[i + 1]] > in gf100_gr_oneinit_tiles()
1952 gr->tpc_nr[gpc_map[i + 0]]) { in gf100_gr_oneinit_tiles()
1954 gpc_map[i + 0] = gpc_map[i + 1]; in gf100_gr_oneinit_tiles()
1961 /* Determine tile->GPC mapping */ in gf100_gr_oneinit_tiles()
1962 mul_factor = gr->gpc_nr * gr->tpc_max; in gf100_gr_oneinit_tiles()
1968 comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor; in gf100_gr_oneinit_tiles()
1970 for (i = 0; i < gr->gpc_nr; i++) { in gf100_gr_oneinit_tiles()
1971 init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor; in gf100_gr_oneinit_tiles()
1972 init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2; in gf100_gr_oneinit_tiles()
1976 for (i = 0; i < gr->tpc_total;) { in gf100_gr_oneinit_tiles()
1977 for (j = 0; j < gr->gpc_nr; j++) { in gf100_gr_oneinit_tiles()
1979 gr->tile[i++] = gpc_map[j]; in gf100_gr_oneinit_tiles()
1980 run_err[j] += init_frac[j] - comm_denom; in gf100_gr_oneinit_tiles()
1992 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_oneinit()
1993 struct nvkm_device *device = subdev->device; in gf100_gr_oneinit()
1994 struct nvkm_intr *intr = &device->mc->intr; in gf100_gr_oneinit()
1998 if (gr->func->oneinit_intr) in gf100_gr_oneinit()
1999 intr = gr->func->oneinit_intr(gr, &intr_type); in gf100_gr_oneinit()
2001 ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev, in gf100_gr_oneinit()
2002 gf100_gr_intr, &gr->base.engine.subdev.inth); in gf100_gr_oneinit()
2006 nvkm_pmu_pgob(device->pmu, false); in gf100_gr_oneinit()
2008 gr->rop_nr = gr->func->rops(gr); in gf100_gr_oneinit()
2009 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; in gf100_gr_oneinit()
2010 for (i = 0; i < gr->gpc_nr; i++) { in gf100_gr_oneinit()
2011 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); in gf100_gr_oneinit()
2012 gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]); in gf100_gr_oneinit()
2013 gr->tpc_total += gr->tpc_nr[i]; in gf100_gr_oneinit()
2014 for (j = 0; j < gr->func->ppc_nr; j++) { in gf100_gr_oneinit()
2015 gr->ppc_tpc_mask[i][j] = in gf100_gr_oneinit()
2016 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); in gf100_gr_oneinit()
2017 if (gr->ppc_tpc_mask[i][j] == 0) in gf100_gr_oneinit()
2020 gr->ppc_nr[i]++; in gf100_gr_oneinit()
2022 gr->ppc_mask[i] |= (1 << j); in gf100_gr_oneinit()
2023 gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]); in gf100_gr_oneinit()
2024 if (gr->ppc_tpc_min == 0 || in gf100_gr_oneinit()
2025 gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j]) in gf100_gr_oneinit()
2026 gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j]; in gf100_gr_oneinit()
2027 if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j]) in gf100_gr_oneinit()
2028 gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j]; in gf100_gr_oneinit()
2031 gr->ppc_total += gr->ppc_nr[i]; in gf100_gr_oneinit()
2036 gr->func->grctx->pagepool_size, 0x100, false, &gr->pagepool); in gf100_gr_oneinit()
2040 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST_SR_LOST, gr->func->grctx->bundle_size, in gf100_gr_oneinit()
2041 0x100, false, &gr->bundle_cb); in gf100_gr_oneinit()
2046 gr->func->grctx->attrib_cb_size(gr), 0x1000, false, &gr->attrib_cb); in gf100_gr_oneinit()
2050 if (gr->func->grctx->unknown_size) { in gf100_gr_oneinit()
2051 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->unknown_size, in gf100_gr_oneinit()
2052 0x100, false, &gr->unknown); in gf100_gr_oneinit()
2057 memset(gr->tile, 0xff, sizeof(gr->tile)); in gf100_gr_oneinit()
2058 gr->func->oneinit_tiles(gr); in gf100_gr_oneinit()
2060 return gr->func->oneinit_sm_id(gr); in gf100_gr_oneinit()
2067 struct nvkm_subdev *subdev = &base->engine.subdev; in gf100_gr_init_()
2068 struct nvkm_device *device = subdev->device; in gf100_gr_init_()
2069 bool reset = device->chipset == 0x137 || device->chipset == 0x138; in gf100_gr_init_()
2075 * frequency when cold-booting a board (ie. returning from D3). in gf100_gr_init_()
2078 * to isolate, with many avenues being dead-ends. in gf100_gr_init_()
2087 reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset); in gf100_gr_init_()
2089 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gf100_gr_init_()
2090 nvkm_rd32(device, 0x000200); in gf100_gr_init_()
2092 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000); in gf100_gr_init_()
2093 nvkm_rd32(device, 0x000200); in gf100_gr_init_()
2096 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); in gf100_gr_init_()
2098 ret = nvkm_falcon_get(&gr->fecs.falcon, subdev); in gf100_gr_init_()
2102 ret = nvkm_falcon_get(&gr->gpccs.falcon, subdev); in gf100_gr_init_()
2106 ret = gr->func->init(gr); in gf100_gr_init_()
2110 nvkm_inth_allow(&subdev->inth); in gf100_gr_init_()
2111 return 0; in gf100_gr_init_()
2118 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_fini()
2120 nvkm_inth_block(&subdev->inth); in gf100_gr_fini()
2122 nvkm_falcon_put(&gr->gpccs.falcon, subdev); in gf100_gr_fini()
2123 nvkm_falcon_put(&gr->fecs.falcon, subdev); in gf100_gr_fini()
2124 return 0; in gf100_gr_fini()
2132 kfree(gr->data); in gf100_gr_dtor()
2134 nvkm_memory_unref(&gr->unknown); in gf100_gr_dtor()
2135 nvkm_memory_unref(&gr->attrib_cb); in gf100_gr_dtor()
2136 nvkm_memory_unref(&gr->bundle_cb); in gf100_gr_dtor()
2137 nvkm_memory_unref(&gr->pagepool); in gf100_gr_dtor()
2139 nvkm_falcon_dtor(&gr->gpccs.falcon); in gf100_gr_dtor()
2140 nvkm_falcon_dtor(&gr->fecs.falcon); in gf100_gr_dtor()
2142 nvkm_blob_dtor(&gr->fecs.inst); in gf100_gr_dtor()
2143 nvkm_blob_dtor(&gr->fecs.data); in gf100_gr_dtor()
2144 nvkm_blob_dtor(&gr->gpccs.inst); in gf100_gr_dtor()
2145 nvkm_blob_dtor(&gr->gpccs.data); in gf100_gr_dtor()
2147 vfree(gr->bundle64); in gf100_gr_dtor()
2148 vfree(gr->bundle_veid); in gf100_gr_dtor()
2149 vfree(gr->bundle); in gf100_gr_dtor()
2150 vfree(gr->method); in gf100_gr_dtor()
2151 vfree(gr->sw_ctx); in gf100_gr_dtor()
2152 vfree(gr->sw_nonctx); in gf100_gr_dtor()
2153 vfree(gr->sw_nonctx1); in gf100_gr_dtor()
2154 vfree(gr->sw_nonctx2); in gf100_gr_dtor()
2155 vfree(gr->sw_nonctx3); in gf100_gr_dtor()
2156 vfree(gr->sw_nonctx4); in gf100_gr_dtor()
2171 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_num_tpc_per_gpc()
2175 for (gpc = 0, i = 0; i < 4; i++) { in gf100_gr_init_num_tpc_per_gpc()
2176 for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) in gf100_gr_init_num_tpc_per_gpc()
2177 data |= gr->tpc_nr[gpc] << (j * 4); in gf100_gr_init_num_tpc_per_gpc()
2179 nvkm_wr32(device, 0x406028 + (i * 4), data); in gf100_gr_init_num_tpc_per_gpc()
2181 nvkm_wr32(device, 0x405870 + (i * 4), data); in gf100_gr_init_num_tpc_per_gpc()
2188 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); in gf100_gr_init_400054()
2194 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_exception2()
2196 nvkm_wr32(device, 0x40011c, 0xffffffff); in gf100_gr_init_exception2()
2197 nvkm_wr32(device, 0x400134, 0xffffffff); in gf100_gr_init_exception2()
2203 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_rop_exceptions()
2206 for (rop = 0; rop < gr->rop_nr; rop++) { in gf100_gr_init_rop_exceptions()
2207 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); in gf100_gr_init_rop_exceptions()
2208 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); in gf100_gr_init_rop_exceptions()
2209 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); in gf100_gr_init_rop_exceptions()
2210 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); in gf100_gr_init_rop_exceptions()
2217 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_shader_exceptions()
2218 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); in gf100_gr_init_shader_exceptions()
2219 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); in gf100_gr_init_shader_exceptions()
2225 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_tex_hww_esr()
2226 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); in gf100_gr_init_tex_hww_esr()
2232 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_419eb4()
2233 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); in gf100_gr_init_419eb4()
2239 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_419cc0()
2242 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gf100_gr_init_419cc0()
2244 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_419cc0()
2245 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) in gf100_gr_init_419cc0()
2246 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); in gf100_gr_init_419cc0()
2253 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); in gf100_gr_init_40601c()
2259 const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001; in gf100_gr_init_fecs_exceptions()
2260 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); in gf100_gr_init_fecs_exceptions()
2266 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_gpc_mmu()
2267 struct nvkm_fb *fb = device->fb; in gf100_gr_init_gpc_mmu()
2269 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001); in gf100_gr_init_gpc_mmu()
2270 nvkm_wr32(device, 0x4188a4, 0x03000000); in gf100_gr_init_gpc_mmu()
2271 nvkm_wr32(device, 0x418888, 0x00000000); in gf100_gr_init_gpc_mmu()
2272 nvkm_wr32(device, 0x41888c, 0x00000000); in gf100_gr_init_gpc_mmu()
2273 nvkm_wr32(device, 0x418890, 0x00000000); in gf100_gr_init_gpc_mmu()
2274 nvkm_wr32(device, 0x418894, 0x00000000); in gf100_gr_init_gpc_mmu()
2275 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8); in gf100_gr_init_gpc_mmu()
2276 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8); in gf100_gr_init_gpc_mmu()
2282 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_num_active_ltcs()
2283 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); in gf100_gr_init_num_active_ltcs()
2289 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_zcull()
2290 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf100_gr_init_zcull()
2291 const u8 tile_nr = ALIGN(gr->tpc_total, 32); in gf100_gr_init_zcull()
2295 for (i = 0; i < tile_nr; i += 8) { in gf100_gr_init_zcull()
2296 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf100_gr_init_zcull()
2297 data |= bank[gr->tile[i + j]] << (j * 4); in gf100_gr_init_zcull()
2298 bank[gr->tile[i + j]]++; in gf100_gr_init_zcull()
2300 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); in gf100_gr_init_zcull()
2303 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init_zcull()
2304 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf100_gr_init_zcull()
2305 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf100_gr_init_zcull()
2306 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf100_gr_init_zcull()
2307 gr->tpc_total); in gf100_gr_init_zcull()
2308 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf100_gr_init_zcull()
2311 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); in gf100_gr_init_zcull()
2317 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_vsc_stream_master()
2318 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); in gf100_gr_init_vsc_stream_master()
2324 struct nvkm_subdev *subdev = &base->engine.subdev; in gf100_gr_reset()
2325 struct nvkm_device *device = subdev->device; in gf100_gr_reset()
2328 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); in gf100_gr_reset()
2332 subdev->func->fini(subdev, false); in gf100_gr_reset()
2333 nvkm_mc_disable(device, subdev->type, subdev->inst); in gf100_gr_reset()
2334 if (gr->func->gpccs.reset) in gf100_gr_reset()
2335 gr->func->gpccs.reset(gr); in gf100_gr_reset()
2337 nvkm_mc_enable(device, subdev->type, subdev->inst); in gf100_gr_reset()
2338 return subdev->func->init(subdev); in gf100_gr_reset()
2344 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init()
2347 nvkm_mask(device, 0x400500, 0x00010001, 0x00000000); in gf100_gr_init()
2349 gr->func->init_gpc_mmu(gr); in gf100_gr_init()
2351 if (gr->sw_nonctx1) { in gf100_gr_init()
2352 gf100_gr_mmio(gr, gr->sw_nonctx1); in gf100_gr_init()
2353 gf100_gr_mmio(gr, gr->sw_nonctx2); in gf100_gr_init()
2354 gf100_gr_mmio(gr, gr->sw_nonctx3); in gf100_gr_init()
2355 gf100_gr_mmio(gr, gr->sw_nonctx4); in gf100_gr_init()
2357 if (gr->sw_nonctx) { in gf100_gr_init()
2358 gf100_gr_mmio(gr, gr->sw_nonctx); in gf100_gr_init()
2360 gf100_gr_mmio(gr, gr->func->mmio); in gf100_gr_init()
2365 if (gr->func->init_r405a14) in gf100_gr_init()
2366 gr->func->init_r405a14(gr); in gf100_gr_init()
2368 if (gr->func->clkgate_pack) in gf100_gr_init()
2369 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack); in gf100_gr_init()
2371 if (gr->func->init_bios) in gf100_gr_init()
2372 gr->func->init_bios(gr); in gf100_gr_init()
2374 gr->func->init_vsc_stream_master(gr); in gf100_gr_init()
2375 gr->func->init_zcull(gr); in gf100_gr_init()
2376 gr->func->init_num_active_ltcs(gr); in gf100_gr_init()
2377 if (gr->func->init_rop_active_fbps) in gf100_gr_init()
2378 gr->func->init_rop_active_fbps(gr); in gf100_gr_init()
2379 if (gr->func->init_bios_2) in gf100_gr_init()
2380 gr->func->init_bios_2(gr); in gf100_gr_init()
2381 if (gr->func->init_swdx_pes_mask) in gf100_gr_init()
2382 gr->func->init_swdx_pes_mask(gr); in gf100_gr_init()
2383 if (gr->func->init_fs) in gf100_gr_init()
2384 gr->func->init_fs(gr); in gf100_gr_init()
2386 nvkm_wr32(device, 0x400500, 0x00010001); in gf100_gr_init()
2388 nvkm_wr32(device, 0x400100, 0xffffffff); in gf100_gr_init()
2389 nvkm_wr32(device, 0x40013c, 0xffffffff); in gf100_gr_init()
2390 nvkm_wr32(device, 0x400124, 0x00000002); in gf100_gr_init()
2392 gr->func->init_fecs_exceptions(gr); in gf100_gr_init()
2394 if (gr->func->init_40a790) in gf100_gr_init()
2395 gr->func->init_40a790(gr); in gf100_gr_init()
2397 if (gr->func->init_ds_hww_esr_2) in gf100_gr_init()
2398 gr->func->init_ds_hww_esr_2(gr); in gf100_gr_init()
2400 nvkm_wr32(device, 0x404000, 0xc0000000); in gf100_gr_init()
2401 nvkm_wr32(device, 0x404600, 0xc0000000); in gf100_gr_init()
2402 nvkm_wr32(device, 0x408030, 0xc0000000); in gf100_gr_init()
2404 if (gr->func->init_40601c) in gf100_gr_init()
2405 gr->func->init_40601c(gr); in gf100_gr_init()
2407 nvkm_wr32(device, 0x406018, 0xc0000000); in gf100_gr_init()
2408 nvkm_wr32(device, 0x404490, 0xc0000000); in gf100_gr_init()
2410 if (gr->func->init_sked_hww_esr) in gf100_gr_init()
2411 gr->func->init_sked_hww_esr(gr); in gf100_gr_init()
2413 nvkm_wr32(device, 0x405840, 0xc0000000); in gf100_gr_init()
2414 nvkm_wr32(device, 0x405844, 0x00ffffff); in gf100_gr_init()
2416 if (gr->func->init_419cc0) in gf100_gr_init()
2417 gr->func->init_419cc0(gr); in gf100_gr_init()
2418 if (gr->func->init_419eb4) in gf100_gr_init()
2419 gr->func->init_419eb4(gr); in gf100_gr_init()
2420 if (gr->func->init_419c9c) in gf100_gr_init()
2421 gr->func->init_419c9c(gr); in gf100_gr_init()
2423 if (gr->func->init_ppc_exceptions) in gf100_gr_init()
2424 gr->func->init_ppc_exceptions(gr); in gf100_gr_init()
2426 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_gr_init()
2427 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_init()
2428 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_init()
2429 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_init()
2430 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_init()
2431 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_gr_init()
2432 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); in gf100_gr_init()
2433 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); in gf100_gr_init()
2434 if (gr->func->init_tex_hww_esr) in gf100_gr_init()
2435 gr->func->init_tex_hww_esr(gr, gpc, tpc); in gf100_gr_init()
2436 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); in gf100_gr_init()
2437 if (gr->func->init_504430) in gf100_gr_init()
2438 gr->func->init_504430(gr, gpc, tpc); in gf100_gr_init()
2439 gr->func->init_shader_exceptions(gr, gpc, tpc); in gf100_gr_init()
2441 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); in gf100_gr_init()
2442 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); in gf100_gr_init()
2445 gr->func->init_rop_exceptions(gr); in gf100_gr_init()
2447 nvkm_wr32(device, 0x400108, 0xffffffff); in gf100_gr_init()
2448 nvkm_wr32(device, 0x400138, 0xffffffff); in gf100_gr_init()
2449 nvkm_wr32(device, 0x400118, 0xffffffff); in gf100_gr_init()
2450 nvkm_wr32(device, 0x400130, 0xffffffff); in gf100_gr_init()
2451 if (gr->func->init_exception2) in gf100_gr_init()
2452 gr->func->init_exception2(gr); in gf100_gr_init()
2454 if (gr->func->init_400054) in gf100_gr_init()
2455 gr->func->init_400054(gr); in gf100_gr_init()
2459 if (gr->func->init_4188a4) in gf100_gr_init()
2460 gr->func->init_4188a4(gr); in gf100_gr_init()
2468 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_reset()
2470 nvkm_wr32(device, 0x409614, 0x00000070); in gf100_gr_fecs_reset()
2472 nvkm_mask(device, 0x409614, 0x00000700, 0x00000700); in gf100_gr_fecs_reset()
2474 nvkm_rd32(device, 0x409614); in gf100_gr_fecs_reset()
2502 if (gr->func->nonstall) in gf100_gr_nonstall()
2503 return gr->func->nonstall(gr); in gf100_gr_nonstall()
2505 return -EINVAL; in gf100_gr_nonstall()
2552 { -1, -1, FERMI_TWOD_A },
2553 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
2554 { -1, -1, FERMI_A, &gf100_fermi },
2555 { -1, -1, FERMI_COMPUTE_A },
2563 gr->firmware = false; in gf100_gr_nofw()
2564 return 0; in gf100_gr_nofw()
2571 struct nvkm_subdev *subdev = &gr->base.engine.subdev; in gf100_gr_load_fw()
2572 struct nvkm_device *device = subdev->device; in gf100_gr_load_fw()
2577 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name); in gf100_gr_load_fw()
2578 ret = request_firmware(&fw, f, device->dev); in gf100_gr_load_fw()
2581 ret = request_firmware(&fw, f, device->dev); in gf100_gr_load_fw()
2588 blob->size = fw->size; in gf100_gr_load_fw()
2589 blob->data = kmemdup(fw->data, blob->size, GFP_KERNEL); in gf100_gr_load_fw()
2591 return (blob->data != NULL) ? 0 : -ENOMEM; in gf100_gr_load_fw()
2597 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_load()
2599 if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false)) in gf100_gr_load()
2600 return -EINVAL; in gf100_gr_load()
2602 if (gf100_gr_load_fw(gr, "fuc409c", &gr->fecs.inst) || in gf100_gr_load()
2603 gf100_gr_load_fw(gr, "fuc409d", &gr->fecs.data) || in gf100_gr_load()
2604 gf100_gr_load_fw(gr, "fuc41ac", &gr->gpccs.inst) || in gf100_gr_load()
2605 gf100_gr_load_fw(gr, "fuc41ad", &gr->gpccs.data)) in gf100_gr_load()
2606 return -ENOENT; in gf100_gr_load()
2608 gr->firmware = true; in gf100_gr_load()
2609 return 0; in gf100_gr_load()
2614 { -1, gf100_gr_load, &gf100_gr },
2615 { -1, gf100_gr_nofw, &gf100_gr },
2627 return -ENOMEM; in gf100_gr_new_()
2628 *pgr = &gr->base; in gf100_gr_new_()
2630 ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base); in gf100_gr_new_()
2634 fwif = nvkm_firmware_load(&gr->base.engine.subdev, fwif, "Gr", gr); in gf100_gr_new_()
2638 gr->func = fwif->func; in gf100_gr_new_()
2640 ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev, in gf100_gr_new_()
2641 "fecs", 0x409000, &gr->fecs.falcon); in gf100_gr_new_()
2645 mutex_init(&gr->fecs.mutex); in gf100_gr_new_()
2647 ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev, in gf100_gr_new_()
2648 "gpccs", 0x41a000, &gr->gpccs.falcon); in gf100_gr_new_()
2652 return 0; in gf100_gr_new_()