39 	u32 invalid[] = { 0, 0, 0, 0 }, *color;  in ga102_gr_zbc_clear_color()
46 	nvkm_mask(device, 0x41bcb4, 0x0000001f, zbc);  in ga102_gr_zbc_clear_color()
47 	nvkm_wr32(device, 0x41bcec, color[0]);  in ga102_gr_zbc_clear_color()
48 	nvkm_wr32(device, 0x41bcf0, color[1]);  in ga102_gr_zbc_clear_color()
49 	nvkm_wr32(device, 0x41bcf4, color[2]);  in ga102_gr_zbc_clear_color()
50 	nvkm_wr32(device, 0x41bcf8, color[3]);  in ga102_gr_zbc_clear_color()
66 	nvkm_wr32(device, 0x41a610, 0x00000000);  in ga102_gr_gpccs_reset()
68 	nvkm_wr32(device, 0x41a610, 0x00000001);  in ga102_gr_gpccs_reset()
74 	.bl_entry = 0x3400,
85 	nvkm_wr32(device, 0x409614, 0x00000010);  in ga102_gr_fecs_reset()
86 	nvkm_wr32(device, 0x41a614, 0x00000020);  in ga102_gr_fecs_reset()
88 	nvkm_wr32(device, 0x409614, 0x00000110);  in ga102_gr_fecs_reset()
89 	nvkm_wr32(device, 0x41a614, 0x00000a20);  in ga102_gr_fecs_reset()
91 	nvkm_rd32(device, 0x409614);  in ga102_gr_fecs_reset()
92 	nvkm_rd32(device, 0x41a614);  in ga102_gr_fecs_reset()
97 	.bl_entry = 0x7e00,
108 	nvkm_wr32(device, 0x41bcbc, 0x40000000);  in ga102_gr_init_rop_exceptions()
109 	nvkm_wr32(device, 0x41bc38, 0x40000000);  in ga102_gr_init_rop_exceptions()
110 	nvkm_wr32(device, 0x41ac94, nvkm_rd32(device, 0x502c94));  in ga102_gr_init_rop_exceptions()
116 	nvkm_wr32(gr->base.engine.subdev.device, 0x40a790, 0xc0000000);  in ga102_gr_init_40a790()
124 	nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);  in ga102_gr_init_gpc_mmu()
125 	nvkm_wr32(device, 0x418894, 0x00000000);  in ga102_gr_init_gpc_mmu()
127 	nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));  in ga102_gr_init_gpc_mmu()
128 	nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));  in ga102_gr_init_gpc_mmu()
129 	nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));  in ga102_gr_init_gpc_mmu()
137 	*pvector = nvkm_rd32(device, 0x400154) & 0x00000fff;  in ga102_gr_oneinit_intr()
144 	return nvkm_rd32(gr->base.engine.subdev.device, 0x400160) & 0x00000fff;  in ga102_gr_nonstall()
254 	pack[0].init = init;  in ga102_gr_av64_to_init()
255 	pack[0].type = 64;  in ga102_gr_av64_to_init()
257 	for (i = 0; i < nent; i++) {  in ga102_gr_av64_to_init()
268 	return 0;  in ga102_gr_av64_to_init()
283 	ret = nvkm_firmware_get(subdev, "gr/NET_img", 0, &fw);  in ga102_gr_load()
291 	for (i = 0; i < net->header.regions; i++) {  in ga102_gr_load()
302 		case  0: fecs_data = reg; break;  in ga102_gr_load()
341 	return 0;  in ga102_gr_load()
346 	{  0, ga102_gr_load, &ga102_gr, &ga102_gr_fecs_acr, &ga102_gr_gpccs_acr },