Lines Matching refs:gr_def
165 gr_def(ctx, 0x4000a4, 0x00000008); in nv40_gr_construct_general()
167 gr_def(ctx, 0x400144, 0x00000001); in nv40_gr_construct_general()
169 gr_def(ctx, 0x400314, 0x00000000); in nv40_gr_construct_general()
173 gr_def(ctx, 0x400514, 0x00040000); in nv40_gr_construct_general()
174 gr_def(ctx, 0x400524, 0x55555555); in nv40_gr_construct_general()
175 gr_def(ctx, 0x400528, 0x55555555); in nv40_gr_construct_general()
176 gr_def(ctx, 0x40052c, 0x55555555); in nv40_gr_construct_general()
177 gr_def(ctx, 0x400530, 0x55555555); in nv40_gr_construct_general()
179 gr_def(ctx, 0x400568, 0x0000ffff); in nv40_gr_construct_general()
180 gr_def(ctx, 0x40056c, 0x0000ffff); in nv40_gr_construct_general()
183 gr_def(ctx, 0x400710, 0x20010001); in nv40_gr_construct_general()
184 gr_def(ctx, 0x400714, 0x0f73ef00); in nv40_gr_construct_general()
186 gr_def(ctx, 0x400724, 0x02008821); in nv40_gr_construct_general()
192 gr_def(ctx, 0x400850, 0x00000040); in nv40_gr_construct_general()
194 gr_def(ctx, 0x400858, 0x00000040); in nv40_gr_construct_general()
195 gr_def(ctx, 0x40085c, 0x00000040); in nv40_gr_construct_general()
196 gr_def(ctx, 0x400864, 0x80000000); in nv40_gr_construct_general()
198 gr_def(ctx, 0x40086c, 0x80000000); in nv40_gr_construct_general()
199 gr_def(ctx, 0x400870, 0x80000000); in nv40_gr_construct_general()
200 gr_def(ctx, 0x400874, 0x80000000); in nv40_gr_construct_general()
201 gr_def(ctx, 0x400878, 0x80000000); in nv40_gr_construct_general()
202 gr_def(ctx, 0x400888, 0x00000040); in nv40_gr_construct_general()
203 gr_def(ctx, 0x40088c, 0x80000000); in nv40_gr_construct_general()
205 gr_def(ctx, 0x4009cc, 0x80000000); in nv40_gr_construct_general()
206 gr_def(ctx, 0x4009dc, 0x80000000); in nv40_gr_construct_general()
211 gr_def(ctx, 0x400860 + (i * 4), 0x00000001); in nv40_gr_construct_general()
213 gr_def(ctx, 0x400880, 0x00000040); in nv40_gr_construct_general()
214 gr_def(ctx, 0x400884, 0x00000040); in nv40_gr_construct_general()
215 gr_def(ctx, 0x400888, 0x00000040); in nv40_gr_construct_general()
217 gr_def(ctx, 0x400894, 0x00000040); in nv40_gr_construct_general()
220 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); in nv40_gr_construct_general()
229 gr_def(ctx, 0x400b0c, 0x0b0b0b0c); in nv40_gr_construct_general()
237 gr_def(ctx, 0x403448, 0x00001010); in nv40_gr_construct_general()
243 gr_def(ctx, 0x403440, 0x00000010); in nv40_gr_construct_general()
248 gr_def(ctx, 0x403440, 0x00003010); in nv40_gr_construct_general()
257 gr_def(ctx, 0x403440, 0x00001010); in nv40_gr_construct_general()
272 gr_def(ctx, 0x401940, 0x00000100); in nv40_gr_construct_state3d()
278 gr_def(ctx, 0x401880 + (i * 4), 0x00000111); in nv40_gr_construct_state3d()
284 gr_def(ctx, 0x401954, 0x00000111); in nv40_gr_construct_state3d()
285 gr_def(ctx, 0x401958, 0x00080060); in nv40_gr_construct_state3d()
286 gr_def(ctx, 0x401974, 0x00000080); in nv40_gr_construct_state3d()
287 gr_def(ctx, 0x401978, 0xffff0000); in nv40_gr_construct_state3d()
288 gr_def(ctx, 0x40197c, 0x00000001); in nv40_gr_construct_state3d()
289 gr_def(ctx, 0x401990, 0x46400000); in nv40_gr_construct_state3d()
297 gr_def(ctx, 0x4019bc, 0xffff0000); in nv40_gr_construct_state3d()
305 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); in nv40_gr_construct_state3d()
309 gr_def(ctx, 0x401a10, 0x0fff0000); in nv40_gr_construct_state3d()
310 gr_def(ctx, 0x401a14, 0x0fff0000); in nv40_gr_construct_state3d()
311 gr_def(ctx, 0x401a1c, 0x00011100); in nv40_gr_construct_state3d()
315 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); in nv40_gr_construct_state3d()
316 gr_def(ctx, 0x401a8c, 0x4b7fffff); in nv40_gr_construct_state3d()
324 gr_def(ctx, 0x401ad0, 0x30201000); in nv40_gr_construct_state3d()
325 gr_def(ctx, 0x401ad4, 0x70605040); in nv40_gr_construct_state3d()
326 gr_def(ctx, 0x401ad8, 0xb8a89888); in nv40_gr_construct_state3d()
327 gr_def(ctx, 0x401adc, 0xf8e8d8c8); in nv40_gr_construct_state3d()
329 gr_def(ctx, 0x401b10, 0x40100000); in nv40_gr_construct_state3d()
331 gr_def(ctx, 0x401b28, device->chipset == 0x40 ? in nv40_gr_construct_state3d()
334 gr_def(ctx, 0x401b34, 0x0000ffff); in nv40_gr_construct_state3d()
335 gr_def(ctx, 0x401b68, 0x435185d6); in nv40_gr_construct_state3d()
336 gr_def(ctx, 0x401b6c, 0x2155b699); in nv40_gr_construct_state3d()
337 gr_def(ctx, 0x401b70, 0xfedcba98); in nv40_gr_construct_state3d()
338 gr_def(ctx, 0x401b74, 0x00000098); in nv40_gr_construct_state3d()
339 gr_def(ctx, 0x401b84, 0xffffffff); in nv40_gr_construct_state3d()
340 gr_def(ctx, 0x401b88, 0x00ff7000); in nv40_gr_construct_state3d()
341 gr_def(ctx, 0x401b8c, 0x0000ffff); in nv40_gr_construct_state3d()
346 gr_def(ctx, 0x401b9c, 0x00ff0000); in nv40_gr_construct_state3d()
348 gr_def(ctx, 0x401be0, 0x00ffff00); in nv40_gr_construct_state3d()
351 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); in nv40_gr_construct_state3d()
352 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); in nv40_gr_construct_state3d()
353 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); in nv40_gr_construct_state3d()
354 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); in nv40_gr_construct_state3d()
355 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); in nv40_gr_construct_state3d()
356 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); in nv40_gr_construct_state3d()
359 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); in nv40_gr_construct_state3d()
360 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); in nv40_gr_construct_state3d()
361 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); in nv40_gr_construct_state3d()
362 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); in nv40_gr_construct_state3d()
365 gr_def(ctx, 0x400f5c, 0x00000002); in nv40_gr_construct_state3d()
379 gr_def(ctx, 0x402404, 0x00000001); in nv40_gr_construct_state3d_2()
384 gr_def(ctx, 0x402404, 0x00000020); in nv40_gr_construct_state3d_2()
389 gr_def(ctx, 0x402404, 0x00000421); in nv40_gr_construct_state3d_2()
392 gr_def(ctx, 0x402404, 0x00000021); in nv40_gr_construct_state3d_2()
395 gr_def(ctx, 0x402408, 0x030c30c3); in nv40_gr_construct_state3d_2()
404 gr_def(ctx, 0x402440, 0x00011001); in nv40_gr_construct_state3d_2()
410 gr_def(ctx, 0x402488, 0x3e020200); in nv40_gr_construct_state3d_2()
411 gr_def(ctx, 0x40248c, 0x00ffffff); in nv40_gr_construct_state3d_2()
414 gr_def(ctx, 0x402490, 0x60103f00); in nv40_gr_construct_state3d_2()
417 gr_def(ctx, 0x402490, 0x40103f00); in nv40_gr_construct_state3d_2()
423 gr_def(ctx, 0x402490, 0x20103f00); in nv40_gr_construct_state3d_2()
426 gr_def(ctx, 0x402490, 0x0c103f00); in nv40_gr_construct_state3d_2()
429 gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? in nv40_gr_construct_state3d_2()
432 gr_def(ctx, 0x402530, 0x00008100); in nv40_gr_construct_state3d_2()
437 gr_def(ctx, 0x402800, 0x00000001); in nv40_gr_construct_state3d_2()
443 gr_def(ctx, 0x402864, 0x00001001); in nv40_gr_construct_state3d_2()
445 gr_def(ctx, 0x402878, 0x00000003); in nv40_gr_construct_state3d_2()
459 gr_def(ctx, 0x402844, 0x00000001); in nv40_gr_construct_state3d_2()
464 gr_def(ctx, 0x402844, 0x00001001); in nv40_gr_construct_state3d_2()
466 gr_def(ctx, 0x402854, 0x00000003); in nv40_gr_construct_state3d_2()
471 gr_def(ctx, 0x402c00, device->chipset == 0x40 ? in nv40_gr_construct_state3d_2()
479 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); in nv40_gr_construct_state3d_2()
481 gr_def(ctx, 0x4030dc, 0x00000005); in nv40_gr_construct_state3d_2()
482 gr_def(ctx, 0x4030e8, 0x0000ffff); in nv40_gr_construct_state3d_2()
497 gr_def(ctx, 0x402cd4, 0x00000005); in nv40_gr_construct_state3d_2()
499 gr_def(ctx, 0x402ce0, 0x0000ffff); in nv40_gr_construct_state3d_2()
507 gr_def(ctx, 0x403420 + (i * 4), 0x00005555); in nv40_gr_construct_state3d_2()
511 gr_def(ctx, 0x403600, 0x00000001); in nv40_gr_construct_state3d_2()
516 gr_def(ctx, 0x403c18, 0x00000001); in nv40_gr_construct_state3d_2()
523 gr_def(ctx, 0x405018, 0x08e00001); in nv40_gr_construct_state3d_2()
525 gr_def(ctx, 0x405c24, 0x000e3000); in nv40_gr_construct_state3d_2()