30 	{ 0x00001000, 64, 0x00100000, 0x00000008 },
31 	{ 0x00000941, 64, 0x00100000, 0x00000000 },
32 	{ 0x0000097e, 64, 0x00100000, 0x00000000 },
33 	{ 0x0000097f, 64, 0x00100000, 0x00000100 },
34 	{ 0x0000035c, 64, 0x00100000, 0x00000000 },
35 	{ 0x0000035d, 64, 0x00100000, 0x00000000 },
36 	{ 0x00000a08, 64, 0x00100000, 0x00000000 },
37 	{ 0x00000a09, 64, 0x00100000, 0x00000000 },
38 	{ 0x00000a0a, 64, 0x00100000, 0x00000000 },
39 	{ 0x00000352, 64, 0x00100000, 0x00000000 },
40 	{ 0x00000353, 64, 0x00100000, 0x00000000 },
41 	{ 0x00000358, 64, 0x00100000, 0x00000000 },
42 	{ 0x00000359, 64, 0x00100000, 0x00000000 },
43 	{ 0x00000370, 64, 0x00100000, 0x00000000 },
44 	{ 0x00000371, 64, 0x00100000, 0x00000000 },
45 	{ 0x00000372, 64, 0x00100000, 0x000fffff },
46 	{ 0x00000366, 64, 0x00100000, 0x00000000 },
47 	{ 0x00000367, 64, 0x00100000, 0x00000000 },
48 	{ 0x00000368, 64, 0x00100000, 0x00000fff },
49 	{ 0x00000623, 64, 0x00100000, 0x00000000 },
50 	{ 0x00000624, 64, 0x00100000, 0x00000000 },
51 	{ 0x0001e100,  1, 0x00000001, 0x02000001 },
69 	const int max_batches = 0xffff;  in gv100_grctx_generate_attrib()
71 	u32 ao = 0;  in gv100_grctx_generate_attrib()
73 	int gpc, ppc, n = 0;  in gv100_grctx_generate_attrib()
75 	gf100_grctx_patch_wr32(chan, 0x405830, attrib);  in gv100_grctx_generate_attrib()
76 	gf100_grctx_patch_wr32(chan, 0x40585c, alpha);  in gv100_grctx_generate_attrib()
77 	gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);  in gv100_grctx_generate_attrib()
79 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {  in gv100_grctx_generate_attrib()
80 		for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {  in gv100_grctx_generate_attrib()
84 			const u32 u = 0x418ea0 + (n * 0x04);  in gv100_grctx_generate_attrib()
85 			const u32 o = PPC_UNIT(gpc, ppc, 0);  in gv100_grctx_generate_attrib()
90 			gf100_grctx_patch_wr32(chan, o + 0xc0, gs);  in gv100_grctx_generate_attrib()
91 			gf100_grctx_patch_wr32(chan, o + 0xf4, bo);  in gv100_grctx_generate_attrib()
92 			gf100_grctx_patch_wr32(chan, o + 0xf0, bs);  in gv100_grctx_generate_attrib()
94 			gf100_grctx_patch_wr32(chan, o + 0xe4, as);  in gv100_grctx_generate_attrib()
95 			gf100_grctx_patch_wr32(chan, o + 0xf8, ao);  in gv100_grctx_generate_attrib()
101 	gf100_grctx_patch_wr32(chan, 0x4181e4, 0x00000100);  in gv100_grctx_generate_attrib()
102 	gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000100);  in gv100_grctx_generate_attrib()
110 	gf100_grctx_patch_wr32(chan, 0x419e00, 0x00000000 | addr >> 12);  in gv100_grctx_generate_attrib_cb()
111 	gf100_grctx_patch_wr32(chan, 0x419e04, 0x80000000 | size >> 7);  in gv100_grctx_generate_attrib_cb()
123 	nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |  in gv100_grctx_generate_rop_mapping()
125 	for (i = 0; i < mapregs; i++) {  in gv100_grctx_generate_rop_mapping()
126 		for (data = 0, j = 0; j < 6; j++)  in gv100_grctx_generate_rop_mapping()
127 			data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);  in gv100_grctx_generate_rop_mapping()
128 		nvkm_wr32(device, 0x418b08 + (i * 4), data);  in gv100_grctx_generate_rop_mapping()
129 		nvkm_wr32(device, 0x41bf00 + (i * 4), data);  in gv100_grctx_generate_rop_mapping()
130 		nvkm_wr32(device, 0x40780c + (i * 4), data);  in gv100_grctx_generate_rop_mapping()
134 	nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |  in gv100_grctx_generate_rop_mapping()
136 	for (i = 0, j = 1; i < 5; i++, j += 4) {  in gv100_grctx_generate_rop_mapping()
137 		u8 v19 = (1 << (j + 0)) % gr->tpc_total;  in gv100_grctx_generate_rop_mapping()
141 		nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |  in gv100_grctx_generate_rop_mapping()
148 	nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |  in gv100_grctx_generate_rop_mapping()
156 	nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);  in gv100_grctx_generate_r400088()
166 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);  in gv100_grctx_generate_sm_id()
167 	nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);  in gv100_grctx_generate_sm_id()
168 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);  in gv100_grctx_generate_sm_id()
175 	nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);  in gv100_grctx_generate_unkn()
176 	nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);  in gv100_grctx_generate_unkn()
177 	nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);  in gv100_grctx_generate_unkn()
178 	nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);  in gv100_grctx_generate_unkn()
179 	nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);  in gv100_grctx_generate_unkn()
186 	const u32 mask = 0x00000010, data = on ? mask : 0x00000000;  in gv100_grctx_unkn88c()
187 	nvkm_mask(device, 0x40988c, mask, data);  in gv100_grctx_unkn88c()
188 	nvkm_rd32(device, 0x40988c);  in gv100_grctx_unkn88c()
189 	nvkm_mask(device, 0x41a88c, mask, data);  in gv100_grctx_unkn88c()
190 	nvkm_rd32(device, 0x41a88c);  in gv100_grctx_unkn88c()
191 	nvkm_mask(device, 0x408a14, mask, data);  in gv100_grctx_unkn88c()
192 	nvkm_rd32(device, 0x408a14);  in gv100_grctx_unkn88c()
202 	.bundle_size = 0x3000,
203 	.bundle_min_gpm_fifo_depth = 0x180,
204 	.bundle_token_limit = 0x1680,
206 	.pagepool_size = 0x20000,
210 	.attrib_nr_max = 0x6c0,
211 	.attrib_nr = 0x480,
212 	.alpha_nr_max = 0xc00,
213 	.alpha_nr = 0x800,
214 	.gfxp_nr = 0xd10,