47 	nvkm_wo32(ramfc, base + 0x00, offset);  in nv40_chan_ramfc_write()
48 	nvkm_wo32(ramfc, base + 0x04, offset);  in nv40_chan_ramfc_write()
49 	nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);  in nv40_chan_ramfc_write()
50 	nvkm_wo32(ramfc, base + 0x18, 0x30000000 |  in nv40_chan_ramfc_write()
57 	nvkm_wo32(ramfc, base + 0x3c, 0x0001ffff);  in nv40_chan_ramfc_write()
59 	return 0;  in nv40_chan_ramfc_write()
65 		{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
66 		{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
67 		{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
68 		{ 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
69 		{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
70 		{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
71 		{ 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
72 		{  2, 28, 0x18, 28, 0x002058 },
73 		{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
74 		{ 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
75 		{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
76 		{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
77 		{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
78 		{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
79 		{ 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
80 		{ 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
81 		{ 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
82 		{ 32,  0, 0x40,  0, 0x0032e4 },
83 		{ 32,  0, 0x44,  0, 0x0032e8 },
84 		{ 32,  0, 0x4c,  0, 0x002088 },
85 		{ 32,  0, 0x50,  0, 0x003300 },
86 		{ 32,  0, 0x54,  0, 0x00330c },
96 	.bar = 0,
97 	.base = 0xc00000,
98 	.size = 0x001000,
130 	u32 inst = 0x00000000, reg, ctx;  in nv40_ectx_bind()
135 		reg = 0x0032e0;  in nv40_ectx_bind()
136 		ctx = 0x38;  in nv40_ectx_bind()
139 		if (WARN_ON(device->chipset < 0x44))  in nv40_ectx_bind()
141 		reg = 0x00330c;  in nv40_ectx_bind()
142 		ctx = 0x54;  in nv40_ectx_bind()
153 	nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);  in nv40_ectx_bind()
155 	chid = nvkm_rd32(device, 0x003204) & (fifo->chid->nr - 1);  in nv40_ectx_bind()
163 	nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);  in nv40_ectx_bind()
190 	nvkm_wr32(device, 0x002040, 0x000000ff);  in nv40_fifo_init()
191 	nvkm_wr32(device, 0x002044, 0x2101ffff);  in nv40_fifo_init()
192 	nvkm_wr32(device, 0x002058, 0x00000001);  in nv40_fifo_init()
194 	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |  in nv40_fifo_init()
200 	case 0x47:  in nv40_fifo_init()
201 	case 0x49:  in nv40_fifo_init()
202 	case 0x4b:  in nv40_fifo_init()
203 		nvkm_wr32(device, 0x002230, 0x00000001);  in nv40_fifo_init()
205 	case 0x40:  in nv40_fifo_init()
206 	case 0x41:  in nv40_fifo_init()
207 	case 0x42:  in nv40_fifo_init()
208 	case 0x43:  in nv40_fifo_init()
209 	case 0x45:  in nv40_fifo_init()
210 	case 0x48:  in nv40_fifo_init()
211 		nvkm_wr32(device, 0x002220, 0x00030002);  in nv40_fifo_init()
214 		nvkm_wr32(device, 0x002230, 0x00000000);  in nv40_fifo_init()
215 		nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +  in nv40_fifo_init()
217 					    0x00030000);  in nv40_fifo_init()
223 	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);  in nv40_fifo_init()
224 	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);  in nv40_fifo_init()
244 	.chan = {{ 0, 0, NV40_CHANNEL_DMA }, &nv40_chan },