56 	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;  in nv04_chan_stop()
67 			u32 rv = (nvkm_rd32(device, c->regp) &  rm) >> c->regs;  in nv04_chan_stop()
234 		u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0);  in nv04_fifo_pause()
239 	if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) &  in nv04_fifo_pause()
280 	u32 engine = nvkm_rd32(device, 0x003280);  in nv04_fifo_swmthd()
288 		data = nvkm_rd32(device, 0x003258) & 0x0000ffff;  in nv04_fifo_swmthd()
309 	u32 pull0 = nvkm_rd32(device, 0x003250);  in nv04_fifo_intr_cache_error()
321 		mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr));  in nv04_fifo_intr_cache_error()
322 		data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr));  in nv04_fifo_intr_cache_error()
324 		mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr));  in nv04_fifo_intr_cache_error()
325 		data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr));  in nv04_fifo_intr_cache_error()
342 		nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1);  in nv04_fifo_intr_cache_error()
345 		nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1);  in nv04_fifo_intr_cache_error()
349 		nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);  in nv04_fifo_intr_cache_error()
358 	u32 dma_get = nvkm_rd32(device, 0x003244);  in nv04_fifo_intr_dma_pusher()
359 	u32 dma_put = nvkm_rd32(device, 0x003240);  in nv04_fifo_intr_dma_pusher()
360 	u32 push = nvkm_rd32(device, 0x003220);  in nv04_fifo_intr_dma_pusher()
361 	u32 state = nvkm_rd32(device, 0x003228);  in nv04_fifo_intr_dma_pusher()
369 		u32 ho_get = nvkm_rd32(device, 0x003328);  in nv04_fifo_intr_dma_pusher()
370 		u32 ho_put = nvkm_rd32(device, 0x003320);  in nv04_fifo_intr_dma_pusher()
371 		u32 ib_get = nvkm_rd32(device, 0x003334);  in nv04_fifo_intr_dma_pusher()
372 		u32 ib_put = nvkm_rd32(device, 0x003330);  in nv04_fifo_intr_dma_pusher()
411 	u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0);  in nv04_fifo_intr()
412 	u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask;  in nv04_fifo_intr()
415 	reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1;  in nv04_fifo_intr()
418 	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;  in nv04_fifo_intr()
419 	get  = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET);  in nv04_fifo_intr()
435 		sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE);  in nv04_fifo_intr()