Lines Matching +full:ch +full:- +full:func
43 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in nv04_chan_stop()
44 struct nvkm_device *device = fifo->engine.subdev.device; in nv04_chan_stop()
45 struct nvkm_memory *fctx = device->imem->ramfc; in nv04_chan_stop()
48 u32 data = chan->ramfc_offset; in nv04_chan_stop()
52 spin_lock_irqsave(&fifo->lock, flags); in nv04_chan_stop()
56 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask; in nv04_chan_stop()
57 if (chid == chan->id) { in nv04_chan_stop()
62 c = chan->func->ramfc->layout; in nv04_chan_stop()
65 u32 rm = ((1ULL << c->bits) - 1) << c->regs; in nv04_chan_stop()
66 u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; in nv04_chan_stop()
67 u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; in nv04_chan_stop()
68 u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm); in nv04_chan_stop()
69 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); in nv04_chan_stop()
70 } while ((++c)->bits); in nv04_chan_stop()
73 c = chan->func->ramfc->layout; in nv04_chan_stop()
75 nvkm_wr32(device, c->regp, 0x00000000); in nv04_chan_stop()
76 } while ((++c)->bits); in nv04_chan_stop()
80 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); in nv04_chan_stop()
86 nvkm_mask(device, NV04_PFIFO_MODE, BIT(chan->id), 0); in nv04_chan_stop()
88 spin_unlock_irqrestore(&fifo->lock, flags); in nv04_chan_stop()
94 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in nv04_chan_start()
97 spin_lock_irqsave(&fifo->lock, flags); in nv04_chan_start()
98 nvkm_mask(fifo->engine.subdev.device, NV04_PFIFO_MODE, BIT(chan->id), BIT(chan->id)); in nv04_chan_start()
99 spin_unlock_irqrestore(&fifo->lock, flags); in nv04_chan_start()
105 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; in nv04_chan_ramfc_clear()
106 const struct nvkm_ramfc_layout *c = chan->func->ramfc->layout; in nv04_chan_ramfc_clear()
110 nvkm_wo32(ramfc, chan->ramfc_offset + c->ctxp, 0x00000000); in nv04_chan_ramfc_clear()
111 } while ((++c)->bits); in nv04_chan_ramfc_clear()
118 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; in nv04_chan_ramfc_write()
119 const u32 base = chan->id * 32; in nv04_chan_ramfc_write()
121 chan->ramfc_offset = base; in nv04_chan_ramfc_write()
126 nvkm_wo32(ramfc, base + 0x08, chan->push->addr >> 4); in nv04_chan_ramfc_write()
183 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in nv04_eobj_ramht_del()
184 struct nvkm_instmem *imem = fifo->engine.subdev.device->imem; in nv04_eobj_ramht_del()
186 mutex_lock(&fifo->mutex); in nv04_eobj_ramht_del()
187 nvkm_ramht_remove(imem->ramht, hash); in nv04_eobj_ramht_del()
188 mutex_unlock(&fifo->mutex); in nv04_eobj_ramht_del()
194 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in nv04_eobj_ramht_add()
195 struct nvkm_instmem *imem = fifo->engine.subdev.device->imem; in nv04_eobj_ramht_add()
196 u32 context = 0x80000000 | chan->id << 24 | engn->id << 16; in nv04_eobj_ramht_add()
199 mutex_lock(&fifo->mutex); in nv04_eobj_ramht_add()
200 hash = nvkm_ramht_insert(imem->ramht, eobj, chan->id, 4, eobj->handle, context); in nv04_eobj_ramht_add()
201 mutex_unlock(&fifo->mutex); in nv04_eobj_ramht_add()
213 __acquires(fifo->lock) in nv04_fifo_pause()
215 struct nvkm_device *device = fifo->engine.subdev.device; in nv04_fifo_pause()
218 spin_lock_irqsave(&fifo->lock, flags); in nv04_fifo_pause()
248 __releases(fifo->lock) in nv04_fifo_start()
250 struct nvkm_device *device = fifo->engine.subdev.device; in nv04_fifo_start()
256 spin_unlock_irqrestore(&fifo->lock, flags); in nv04_fifo_start()
276 struct nvkm_sw *sw = device->sw; in nv04_fifo_swmthd()
284 case 0x0000 ... 0x0000: /* subchannel's engine -> software */ in nv04_fifo_swmthd()
287 case 0x0180 ... 0x01fc: /* handle -> instance */ in nv04_fifo_swmthd()
305 struct nvkm_subdev *subdev = &fifo->engine.subdev; in nv04_fifo_intr_cache_error()
306 struct nvkm_device *device = subdev->device; in nv04_fifo_intr_cache_error()
320 if (device->card_type < NV_40) { in nv04_fifo_intr_cache_error()
330 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); in nv04_fifo_intr_cache_error()
331 nvkm_error(subdev, "CACHE_ERROR - " in nv04_fifo_intr_cache_error()
332 "ch %d [%s] subc %d mthd %04x data %08x\n", in nv04_fifo_intr_cache_error()
333 chid, chan ? chan->name : "unknown", in nv04_fifo_intr_cache_error()
356 struct nvkm_subdev *subdev = &fifo->engine.subdev; in nv04_fifo_intr_dma_pusher()
357 struct nvkm_device *device = subdev->device; in nv04_fifo_intr_dma_pusher()
366 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); in nv04_fifo_intr_dma_pusher()
367 name = chan ? chan->name : "unknown"; in nv04_fifo_intr_dma_pusher()
368 if (device->card_type == NV_50) { in nv04_fifo_intr_dma_pusher()
374 nvkm_error(subdev, "DMA_PUSHER - " in nv04_fifo_intr_dma_pusher()
375 "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x " in nv04_fifo_intr_dma_pusher()
390 nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x " in nv04_fifo_intr_dma_pusher()
409 struct nvkm_subdev *subdev = &fifo->engine.subdev; in nv04_fifo_intr()
410 struct nvkm_device *device = subdev->device; in nv04_fifo_intr()
418 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask; in nv04_fifo_intr()
442 if (device->card_type == NV_50) { in nv04_fifo_intr()
450 nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT); in nv04_fifo_intr()
468 struct nvkm_device *device = fifo->engine.subdev.device; in nv04_fifo_init()
469 struct nvkm_instmem *imem = device->imem; in nv04_fifo_init()
470 struct nvkm_ramht *ramht = imem->ramht; in nv04_fifo_init()
471 struct nvkm_memory *ramro = imem->ramro; in nv04_fifo_init()
472 struct nvkm_memory *ramfc = imem->ramfc; in nv04_fifo_init()
478 ((ramht->bits - 9) << 16) | in nv04_fifo_init()
479 (ramht->gpuobj->addr >> 8)); in nv04_fifo_init()
483 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); in nv04_fifo_init()
502 nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_SW, 0); in nv04_fifo_runl_ctor()
503 nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_DMAOBJ, 0); in nv04_fifo_runl_ctor()
504 nvkm_runl_add(runl, 1, fifo->func->engn , NVKM_ENGINE_GR, 0); in nv04_fifo_runl_ctor()
505 nvkm_runl_add(runl, 2, fifo->func->engn , NVKM_ENGINE_MPEG, 0); /* NV31- */ in nv04_fifo_runl_ctor()
513 return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr - 1, &fifo->chid); in nv04_fifo_chid_ctor()