engine/fifo/gp100.c

35 	nvkm_wo32(memory, offset + 0, chan->id | chan->runq << 14);  in gp100_runl_insert_chan()
57 	{ 0x01, "DISPLAY" },
58 	{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
59 	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
60 	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
61 	{ 0x06, "HOST0" },
62 	{ 0x07, "HOST1" },
63 	{ 0x08, "HOST2" },
64 	{ 0x09, "HOST3" },
65 	{ 0x0a, "HOST4" },
66 	{ 0x0b, "HOST5" },
67 	{ 0x0c, "HOST6" },
68 	{ 0x0d, "HOST7" },
69 	{ 0x0e, "HOST8" },
70 	{ 0x0f, "HOST9" },
71 	{ 0x10, "HOST10" },
72 	{ 0x13, "PERF" },
73 	{ 0x17, "PMU" },
74 	{ 0x18, "PTP" },
75 	{ 0x1f, "PHYSICAL" },
93 	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));  in gp100_fifo_intr_mmu_fault_unit()
94 	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));  in gp100_fifo_intr_mmu_fault_unit()
95 	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));  in gp100_fifo_intr_mmu_fault_unit()
96 	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));  in gp100_fifo_intr_mmu_fault_unit()
101 	info.time   = 0;  in gp100_fifo_intr_mmu_fault_unit()
104 	info.gpc    = (type & 0x1f000000) >> 24;  in gp100_fifo_intr_mmu_fault_unit()
105 	info.hub    = (type & 0x00100000) >> 20;  in gp100_fifo_intr_mmu_fault_unit()
106 	info.access = (type & 0x00070000) >> 16;  in gp100_fifo_intr_mmu_fault_unit()
107 	info.client = (type & 0x00007f00) >> 8;  in gp100_fifo_intr_mmu_fault_unit()
108 	info.reason = (type & 0x0000001f);  in gp100_fifo_intr_mmu_fault_unit()
130 	.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp, .force = true },
131 	.chan = {{ 0, 0, PASCAL_CHANNEL_GPFIFO_A }, &gm107_chan },