39 	nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark);  in g94_sor_dp_watermark()
49 	nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2);  in g94_sor_dp_activesym()
50 	nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | VTUf << 16 | VTUi << 8);  in g94_sor_dp_activesym()
59 	nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h);  in g94_sor_dp_audio_sym()
60 	nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v);  in g94_sor_dp_audio_sym()
71 	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);  in g94_sor_dp_drive()
72 	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);  in g94_sor_dp_drive()
73 	data[2] = nvkm_rd32(device, 0x61c130 + loff);  in g94_sor_dp_drive()
74 	if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)  in g94_sor_dp_drive()
75 		data[2] = (data[2] & ~0x0000ff00) | (pu << 8);  in g94_sor_dp_drive()
77 	nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));  in g94_sor_dp_drive()
78 	nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));  in g94_sor_dp_drive()
79 	nvkm_wr32(device, 0x61c130 + loff, data[2]);  in g94_sor_dp_drive()
90 	case 0: data = 0x00001000; break;  in g94_sor_dp_pattern()
91 	case 1: data = 0x01000000; break;  in g94_sor_dp_pattern()
92 	case 2: data = 0x02000000; break;  in g94_sor_dp_pattern()
98 	nvkm_mask(device, 0x61c10c + loff, 0x0f001000, data);  in g94_sor_dp_pattern()
107 	u32 mask = 0, i;  in g94_sor_dp_power()
109 	for (i = 0; i < nr; i++)  in g94_sor_dp_power()
112 	nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);  in g94_sor_dp_power()
113 	nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);  in g94_sor_dp_power()
115 		if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))  in g94_sor_dp_power()
126 	u32 dpctrl = 0x00000000;  in g94_sor_dp_links()
127 	u32 clksor = 0x00000000;  in g94_sor_dp_links()
131 		dpctrl |= 0x00004000;  in g94_sor_dp_links()
132 	if (sor->dp.bw > 0x06)  in g94_sor_dp_links()
133 		clksor |= 0x00040000;  in g94_sor_dp_links()
135 	nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor);  in g94_sor_dp_links()
136 	nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl);  in g94_sor_dp_links()
137 	return 0;  in g94_sor_dp_links()
142 	.lanes = { 2, 1, 0, 3},
159 		switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) {  in g94_sor_war_needed()
160 		case 0x00000000:  in g94_sor_war_needed()
161 		case 0x00030000:  in g94_sor_war_needed()
183 		clksor = nvkm_rd32(device, 0x614300 + nv50_ior_base(ior));  in g94_sor_war_update_sppll1()
184 		switch (clksor & 0x03000000) {  in g94_sor_war_update_sppll1()
185 		case 0x02000000:  in g94_sor_war_update_sppll1()
186 		case 0x03000000:  in g94_sor_war_update_sppll1()
197 	nvkm_mask(device, 0x00e840, 0x80000000, 0x00000000);  in g94_sor_war_update_sppll1()
210 	sorpwr = nvkm_rd32(device, 0x61c004 + soff);  in g94_sor_war_3()
211 	if (sorpwr & 0x00000001) {  in g94_sor_war_3()
212 		u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);  in g94_sor_war_3()
213 		u32  pd_pc = (seqctl & 0x00000f00) >> 8;  in g94_sor_war_3()
214 		u32  pu_pc =  seqctl & 0x0000000f;  in g94_sor_war_3()
216 		nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x1f008000);  in g94_sor_war_3()
219 			if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))  in g94_sor_war_3()
222 		nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000);  in g94_sor_war_3()
224 			if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))  in g94_sor_war_3()
228 		nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x00002000);  in g94_sor_war_3()
229 		nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f000000);  in g94_sor_war_3()
232 	nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000000);  in g94_sor_war_3()
233 	nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x00000000);  in g94_sor_war_3()
235 	if (sorpwr & 0x00000001)  in g94_sor_war_3()
236 		nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000001);  in g94_sor_war_3()
250 	nvkm_mask(device, 0x00e840, 0x80000000, 0x80000000);  in g94_sor_war_2()
251 	nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x03000000);  in g94_sor_war_2()
252 	nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000001);  in g94_sor_war_2()
254 	nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x00000000);  in g94_sor_war_2()
255 	nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x14000000);  in g94_sor_war_2()
257 	nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x00000000);  in g94_sor_war_2()
258 	nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x01000000);  in g94_sor_war_2()
260 	if (nvkm_rd32(device, 0x61c004 + soff) & 0x00000001) {  in g94_sor_war_2()
261 		u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);  in g94_sor_war_2()
262 		u32  pu_pc = seqctl & 0x0000000f;  in g94_sor_war_2()
263 		nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f008000);  in g94_sor_war_2()
272 	u32 ctrl = nvkm_rd32(device, 0x610794 + coff);  in g94_sor_state()
274 	state->proto_evo = (ctrl & 0x00000f00) >> 8;  in g94_sor_state()
276 	case 0: state->proto = LVDS; state->link = 1; break;  in g94_sor_state()
287 	state->head = ctrl & 0x00000003;  in g94_sor_state()
314 	*pmask = (nvkm_rd32(device, 0x610184) & 0x0f000000) >> 24;  in g94_sor_cnt()
320 	.mthd = 0x0040,
321 	.addr = 0x000008,
323 		{ 0x0600, 0x610794 },
331 	.addr = 0x000000,
332 	.prev = 0x000004,
346 	.ctrl = 0,
347 	.user = 0,
363 	.root = { 0,0,GT206_DISP },
365 		{{0,0,  G82_DISP_CURSOR             }, nvkm_disp_chan_new, & nv50_disp_curs },
366 		{{0,0,  G82_DISP_OVERLAY            }, nvkm_disp_chan_new, & nv50_disp_oimm },
367 		{{0,0,GT200_DISP_BASE_CHANNEL_DMA   }, nvkm_disp_chan_new, &  g84_disp_base },
368 		{{0,0,GT206_DISP_CORE_CHANNEL_DMA   }, nvkm_disp_core_new, &  g94_disp_core },
369 		{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &gt200_disp_ovly },