Lines Matching +full:0 +full:x0007ffff
32 ctx_object: .b32 0
35 ctx_dma_query: .b32 0
36 ctx_dma_src: .b32 0
37 ctx_dma_dst: .b32 0
40 ctx_query_address_high: .b32 0
41 ctx_query_address_low: .b32 0
42 ctx_query_counter: .b32 0
43 ctx_src_address_high: .b32 0
44 ctx_src_address_low: .b32 0
45 ctx_src_pitch: .b32 0
46 ctx_src_tile_mode: .b32 0
47 ctx_src_xsize: .b32 0
48 ctx_src_ysize: .b32 0
49 ctx_src_zsize: .b32 0
50 ctx_src_zoff: .b32 0
51 ctx_src_xoff: .b32 0
52 ctx_src_yoff: .b32 0
53 ctx_src_cpp: .b32 0
54 ctx_dst_address_high: .b32 0
55 ctx_dst_address_low: .b32 0
56 ctx_dst_pitch: .b32 0
57 ctx_dst_tile_mode: .b32 0
58 ctx_dst_xsize: .b32 0
59 ctx_dst_ysize: .b32 0
60 ctx_dst_zsize: .b32 0
61 ctx_dst_zoff: .b32 0
62 ctx_dst_xoff: .b32 0
63 ctx_dst_yoff: .b32 0
64 ctx_dst_cpp: .b32 0
65 ctx_format: .b32 0
66 ctx_swz_const0: .b32 0
67 ctx_swz_const1: .b32 0
68 ctx_xcnt: .b32 0
69 ctx_ycnt: .b32 0
73 // mthd 0x0000, NAME
74 .b16 0x000 1
75 .b32 #ctx_object ~0xffffffff
76 // mthd 0x0100, NOP
77 .b16 0x040 1
78 .b32 0x00010000 + #cmd_nop ~0xffffffff
79 // mthd 0x0140, PM_TRIGGER
80 .b16 0x050 1
81 .b32 0x00010000 + #cmd_pm_trigger ~0xffffffff
83 // mthd 0x0180-0x018c, DMA_
84 .b16 0x060 #ctx_dma_count
86 .b32 0x00010000 + #cmd_dma ~0xffffffff
87 .b32 0x00010000 + #cmd_dma ~0xffffffff
88 .b32 0x00010000 + #cmd_dma ~0xffffffff
90 // mthd 0x0200-0x0218, SRC_TILE
91 .b16 0x80 7
92 .b32 #ctx_src_tile_mode ~0x00000fff
93 .b32 #ctx_src_xsize ~0x0007ffff
94 .b32 #ctx_src_ysize ~0x00001fff
95 .b32 #ctx_src_zsize ~0x000007ff
96 .b32 #ctx_src_zoff ~0x00000fff
97 .b32 #ctx_src_xoff ~0x0007ffff
98 .b32 #ctx_src_yoff ~0x00001fff
99 // mthd 0x0220-0x0238, DST_TILE
100 .b16 0x88 7
101 .b32 #ctx_dst_tile_mode ~0x00000fff
102 .b32 #ctx_dst_xsize ~0x0007ffff
103 .b32 #ctx_dst_ysize ~0x00001fff
104 .b32 #ctx_dst_zsize ~0x000007ff
105 .b32 #ctx_dst_zoff ~0x00000fff
106 .b32 #ctx_dst_xoff ~0x0007ffff
107 .b32 #ctx_dst_yoff ~0x00001fff
108 // mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
109 .b16 0xc0 2
110 .b32 0x00010000 + #cmd_exec ~0xffffffff
111 .b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff
112 // mthd 0x030c-0x0340, various stuff
113 .b16 0xc3 14
114 .b32 #ctx_src_address_high ~0x000000ff
115 .b32 #ctx_src_address_low ~0xffffffff
116 .b32 #ctx_dst_address_high ~0x000000ff
117 .b32 #ctx_dst_address_low ~0xffffffff
118 .b32 #ctx_src_pitch ~0x0007ffff
119 .b32 #ctx_dst_pitch ~0x0007ffff
120 .b32 #ctx_xcnt ~0x0000ffff
121 .b32 #ctx_ycnt ~0x00001fff
122 .b32 #ctx_format ~0x0333ffff
123 .b32 #ctx_swz_const0 ~0xffffffff
124 .b32 #ctx_swz_const1 ~0xffffffff
125 .b32 #ctx_query_address_high ~0x000000ff
126 .b32 #ctx_query_address_low ~0xffffffff
127 .b32 #ctx_query_counter ~0xffffffff
128 .b16 0x800 0
143 mov $r1 0x400
144 movw $r2 0xfff3
145 sethi $r2 0
146 iowr I[$r1 + 0x300] $r2
149 or $r2 0xc
154 mov $r1 0x1200
166 iord $r1 I[$r0 + 0x200]
168 and $r2 $r1 0x00000008
172 and $r2 $r1 0x00000004
177 and $r1 $r1 0x0000000c
178 iowr I[$r0 + 0x100] $r1
181 // $p1 direction (0 = unload, 1 = load)
184 mov $r4 0x7700
191 mov $r4 0x2100
192 iord $r4 I[$r4 + 0]
195 add b32 $r4 0x30
198 mov $r15 0x61c
200 mov $r5 0x114
209 sub b32 $r5 0x100
210 mov $r6 0xff
213 sethi $r5 0x00020000
216 sethi $r5 0
219 mov $r14 0
221 ld b32 $r4 D[$r5 + 0]
230 sethi $r4 0x60000
244 mov $r2 0x1400
248 xbit $r15 $r3 0x1e
252 bclr $r3 0x1e
255 iowr I[$r2 + 0x200] $r4
260 iord $r3 I[$r2 + 0x100]
263 xbit $r13 $r3 0x1e
273 add b32 $r8 $r6 0x180
281 iowr I[$r2 + 0x200] $r3
286 mov $r3 0x1900
287 iord $r2 I[$r3 + 0x100]
288 iord $r3 I[$r3 + 0x000]
289 and $r4 $r2 0x7ff
291 shl b32 $r2 0x10
298 ld b16 $r6 D[$r5 + 0]
318 cmpu b32 $r5 0
322 ld b16 $r5 D[$r4 + 0]
324 cmpu b32 $r6 0
341 mov $r4 0x1000
342 iowr I[$r4 + 0x000] $r2
343 iowr I[$r4 + 0x100] $r3
344 mov $r2 0x40
347 iord $r2 I[$r0 + 0x200]
348 and $r2 0x40
349 cmpu b32 $r2 0
353 mov $r2 0x1d00
386 mov $r2 0x2200
388 sethi $r3 0x20000
408 bset $r3 0x1e
410 add b32 $r4 0x600
420 add $sp -0x10
421 st b32 D[$sp + 0x00] $r0
422 st b32 D[$sp + 0x04] $r0
423 st b32 D[$sp + 0x08] $r0
424 st b32 D[$sp + 0x0c] $r0
440 and $r10 $r4 0xf
452 mov $r12 0x10
458 mov $r12 0x14
462 mov $r12 0x80
473 // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
486 mov $r5 0x810
488 iowr I[$r5 + 0x000] $r6
489 iowr I[$r5 + 0x100] $r7
490 add b32 $r5 0x800
497 iowr I[$r5 + 0x000] $r6
498 add b32 $r5 0x100
499 ld b32 $r6 D[$sp + 0x00]
500 iowr I[$r5 + 0x000] $r6
501 ld b32 $r6 D[$sp + 0x04]
502 iowr I[$r5 + 0x100] $r6
503 ld b32 $r6 D[$sp + 0x08]
504 iowr I[$r5 + 0x200] $r6
505 ld b32 $r6 D[$sp + 0x0c]
506 iowr I[$r5 + 0x300] $r6
507 add b32 $r5 0x400
509 iowr I[$r5 + 0x000] $r6
511 iowr I[$r5 + 0x100] $r6
512 add $sp 0x10
534 // $r4: hw command (0x104800)
548 extr $r7 $r7 0:3
549 cmp b32 $r7 0xe
586 add b32 $r6 0x208
588 iowr I[$r6 + 0x000] $r15
649 iowr I[$r6 + 0x200] $r9
651 // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff
657 adc b32 $r8 0
660 sub b32 $r6 0x600
661 iowr I[$r6 + 0x000] $r7
662 add b32 $r6 0x400
663 iowr I[$r6 + 0x000] $r8
672 add b32 $r6 0x202
675 iowr I[$r6 + 0x000] $r7
676 add b32 $r6 0x400
679 iowr I[$r6 + 0x000] $r7
680 add b32 $r6 0x400
682 iowr I[$r6 + 0x000] $r7
689 mov $r0 0x800
700 // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
704 mov $r4 0x80c
708 iowr I[$r4 + 0x000] $r5
709 iowr I[$r4 + 0x100] $r0
710 mov $r5 0xc
711 iowr I[$r4 + 0x200] $r5
712 add b32 $r4 0x400
715 iowr I[$r4 + 0x000] $r5
716 add b32 $r4 0x500
717 mov $r5 0x00000b00
718 sethi $r5 0x00010000
719 iowr I[$r4 + 0x000] $r5
720 mov $r5 0x00004040
722 sethi $r5 0x80800000
723 iowr I[$r4 + 0x100] $r5
724 mov $r5 0x00001110
725 sethi $r5 0x13120000
726 iowr I[$r4 + 0x200] $r5
727 mov $r5 0x00001514
728 sethi $r5 0x17160000
729 iowr I[$r4 + 0x300] $r5
730 mov $r5 0x00002601
731 sethi $r5 0x00010000
732 mov $r4 0x800
734 iowr I[$r4 + 0x000] $r5
739 mov $r4 0x80c
742 iowr I[$r4 + 0x000] $r5
743 iowr I[$r4 + 0x100] $r0
744 mov $r5 0x4
745 iowr I[$r4 + 0x200] $r5
746 add b32 $r4 0x400
749 iowr I[$r4 + 0x000] $r5
750 add b32 $r4 0x500
751 mov $r5 0x00000300
752 iowr I[$r4 + 0x000] $r5
753 mov $r5 0x00001110
754 sethi $r5 0x13120000
755 iowr I[$r4 + 0x100] $r5
757 add b32 $r4 0x500
758 iowr I[$r4 + 0x000] $r5
759 mov $r5 0x00002601
760 sethi $r5 0x00010000
761 mov $r4 0x800
763 iowr I[$r4 + 0x000] $r5
788 xbit $r15 $r3 0
791 mov $r4 0x200
794 mov $r6 0x810
800 iowr I[$r6 + 0x000] $r7
801 iowr I[$r6 + 0x100] $r7
827 mov $r5 0x800
830 iowr I[$r5 + 0x100] $r6
831 mov $r6 0x0041
833 sethi $r6 0x44000000
858 mov $r2 0x2200
860 sethi $r3 0x10000
864 .align 0x100