Lines Matching +full:0 +full:x00001400
37 #define NV_CIO_CRE_44_HEADA 0x0
38 #define NV_CIO_CRE_44_HEADB 0x3
39 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
53 uint8_t sum = 0; in nv_cksum()
55 for (i = 0; i < length; i++) in nv_cksum()
66 int compare_record_len, i = 0; in clkcmptable()
67 uint16_t compareclk, scriptptr = 0; in clkcmptable()
96 NV_INFO(drm, "0x%04X: Parsing digital output script table\n", in run_digital_op_script()
98 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB : in run_digital_op_script()
109 …bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0); in call_lvds_manufacturer_script()
127 (pdev->device == 0x0179 || pdev->device == 0x0189 || in call_lvds_manufacturer_script()
128 pdev->device == 0x0329)) in call_lvds_manufacturer_script()
129 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); in call_lvds_manufacturer_script()
132 return 0; in call_lvds_manufacturer_script()
149 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; in run_lvds_table()
150 uint16_t scriptptr = 0, clktable; in run_lvds_table()
205 return 0; in run_lvds_table()
224 (lvds_ver >= 0x30 && script == LVDS_INIT)) in call_lvds_script()
225 return 0; in call_lvds_script()
240 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in call_lvds_script()
242 if (lvds_ver < 0x30) in call_lvds_script()
249 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; in call_lvds_script()
250 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); in call_lvds_script()
252 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); in call_lvds_script()
264 * BMP version (0xa) LVDS table has a simple header of version and in parse_lvds_manufacturer_table_header()
273 memset(lth, 0, sizeof(struct lvdstableheader)); in parse_lvds_manufacturer_table_header()
275 if (bios->fp.lvdsmanufacturerpointer == 0x0) { in parse_lvds_manufacturer_table_header()
283 case 0x0a: /* pre NV40 */ in parse_lvds_manufacturer_table_header()
287 case 0x30: /* NV4x */ in parse_lvds_manufacturer_table_header()
289 if (headerlen < 0x1f) { in parse_lvds_manufacturer_table_header()
295 case 0x40: /* G80/G90 */ in parse_lvds_manufacturer_table_header()
297 if (headerlen < 0x7) { in parse_lvds_manufacturer_table_header()
306 lvds_ver >> 4, lvds_ver & 0xf); in parse_lvds_manufacturer_table_header()
314 return 0; in parse_lvds_manufacturer_table_header()
326 * Internal_Flags struct at 0x48 is set, the user strap gets overriden in get_fp_strap()
328 * strap has been committed to CR58 for CR57=0xf on head A, which may be in get_fp_strap()
332 if (bios->major_version < 5 && bios->data[0x48] & 0x4) in get_fp_strap()
333 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; in get_fp_strap()
336 return nvif_rd32(device, 0x001800) & 0x0000000f; in get_fp_strap()
339 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; in get_fp_strap()
341 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; in get_fp_strap()
348 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; in parse_fp_mode_table()
352 if (bios->fp.fptablepointer == 0x0) { in parse_fp_mode_table()
355 bios->digital_min_front_porch = 0x4b; in parse_fp_mode_table()
356 return 0; in parse_fp_mode_table()
360 fptable_ver = fptable[0]; in parse_fp_mode_table()
364 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no in parse_fp_mode_table()
367 * though). Here we assume that a version of 0x05 matches this case in parse_fp_mode_table()
369 * common case for the panel type field is 0x0005, and that is in in parse_fp_mode_table()
372 case 0x05: /* some NV10, 11, 15, 16 */ in parse_fp_mode_table()
376 case 0x10: /* some NV15/16, and NV11+ */ in parse_fp_mode_table()
378 ofs = 0; in parse_fp_mode_table()
380 case 0x20: /* NV40+ */ in parse_fp_mode_table()
394 fptable_ver >> 4, fptable_ver & 0xf); in parse_fp_mode_table()
399 return 0; in parse_fp_mode_table()
405 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { in parse_fp_mode_table()
410 if (bios->fp.fpxlatetableptr == 0x0) { in parse_fp_mode_table()
425 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ in parse_fp_mode_table()
426 if (lth.lvds_ver > 0x10) in parse_fp_mode_table()
427 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; in parse_fp_mode_table()
430 * If either the strap or xlated fpindex value are 0xf there is no in parse_fp_mode_table()
434 if (fpstrapping == 0xf || fpindex == 0xf) in parse_fp_mode_table()
435 return 0; in parse_fp_mode_table()
445 return 0; in parse_fp_mode_table()
457 memset(mode, 0, sizeof(struct drm_display_mode)); in nouveau_bios_fp_mode()
459 * For version 1.0 (version in byte 0): in nouveau_bios_fp_mode()
479 mode->flags |= (mode_entry[37] & 0x10) ? in nouveau_bios_fp_mode()
481 mode->flags |= (mode_entry[37] & 0x1) ? in nouveau_bios_fp_mode()
503 * Following the header, the BMP (ver 0xa) table has several records, in nouveau_bios_parse_lvds_table()
523 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; in nouveau_bios_parse_lvds_table()
533 case 0x0a: /* pre NV40 */ in nouveau_bios_parse_lvds_table()
542 if (chip_version < 0x25) { in nouveau_bios_parse_lvds_table()
550 2 : 0; in nouveau_bios_parse_lvds_table()
553 } else if (chip_version < 0x30) { in nouveau_bios_parse_lvds_table()
560 * table?)), setting an lvdsmanufacturerindex of 0 and in nouveau_bios_parse_lvds_table()
561 * an fp strap of the match index (or 0xf if none) in nouveau_bios_parse_lvds_table()
563 lvdsmanufacturerindex = 0; in nouveau_bios_parse_lvds_table()
566 lvdsmanufacturerindex = 0; in nouveau_bios_parse_lvds_table()
578 case 0x30: /* NV4x */ in nouveau_bios_parse_lvds_table()
579 case 0x40: /* G80/G90 */ in nouveau_bios_parse_lvds_table()
589 case 0x0a: in nouveau_bios_parse_lvds_table()
596 case 0x30: in nouveau_bios_parse_lvds_table()
597 case 0x40: in nouveau_bios_parse_lvds_table()
617 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) in nouveau_bios_parse_lvds_table()
622 return 0; in nouveau_bios_parse_lvds_table()
640 uint16_t clktable = 0, scriptptr; in run_tmds_table()
644 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && in run_tmds_table()
646 return 0; in run_tmds_table()
671 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in run_tmds_table()
673 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; in run_tmds_table()
674 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); in run_tmds_table()
676 return 0; in run_tmds_table()
684 * offset + 0 (16 bits): init script tables pointer in parse_script_table_pointers()
701 * offset + 0 (16 bits): loadval table pointer in parse_bit_A_tbl_entry()
715 if (load_table_ptr == 0x0) { in parse_bit_A_tbl_entry()
722 if (version != 0x10) { in parse_bit_A_tbl_entry()
724 version >> 4, version & 0xF); in parse_bit_A_tbl_entry()
738 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; in parse_bit_A_tbl_entry()
740 return 0; in parse_bit_A_tbl_entry()
749 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte in parse_bit_display_tbl_entry()
762 return 0; in parse_bit_display_tbl_entry()
780 return 0; in parse_bit_init_tbl_entry()
788 * offset + 0 (32 bits): BIOS version dword (as in B table) in parse_bit_i_tbl_entry()
822 return 0; in parse_bit_i_tbl_entry()
833 if (dacver != 0x00 && dacver != 0x10) { in parse_bit_i_tbl_entry()
835 "%d.%d not known\n", dacver >> 4, dacver & 0xf); in parse_bit_i_tbl_entry()
842 return 0; in parse_bit_i_tbl_entry()
851 * offset + 0 (16 bits): LVDS strap xlate table pointer in parse_bit_lvds_tbl_entry()
867 return 0; in parse_bit_lvds_tbl_entry()
888 if (bitentry->length < 0x5) in parse_bit_M_tbl_entry()
889 return 0; in parse_bit_M_tbl_entry()
895 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; in parse_bit_M_tbl_entry()
899 return 0; in parse_bit_M_tbl_entry()
909 * offset + 0 (16 bits): TMDS table pointer in parse_bit_tmds_tbl_entry()
912 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being in parse_bit_tmds_tbl_entry()
942 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); in parse_bit_tmds_tbl_entry()
944 /* nv50+ has v2.0, but we don't parse it atm */ in parse_bit_tmds_tbl_entry()
945 if (bios->data[tmdstableptr] != 0x11) in parse_bit_tmds_tbl_entry()
960 return 0; in parse_bit_tmds_tbl_entry()
983 if (entry[0] == id) { in bit_table()
984 bit->id = entry[0]; in bit_table()
989 return 0; in bit_table()
1006 if (bit_table(dev, table->id, &bitentry) == 0) in parse_bit_table()
1027 if (bios->major_version >= 0x60) /* g80+ */ in parse_bit_structure()
1037 return 0; in parse_bit_structure()
1061 * offset + 58: write CRTC index for I2C pair 0 in parse_bmp_structure()
1062 * offset + 59: read CRTC index for I2C pair 0 in parse_bmp_structure()
1091 bios->digital_min_front_porch = 0x4b; in parse_bmp_structure()
1103 * Make sure that 0x36 is blank and can't be mistaken for a DCB in parse_bmp_structure()
1107 *(uint16_t *)&bios->data[0x36] = 0; in parse_bmp_structure()
1120 if (bmp_version_major == 0) in parse_bmp_structure()
1122 return 0; in parse_bmp_structure()
1130 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) in parse_bmp_structure()
1134 else if (bmp_version_minor < 0x6) in parse_bmp_structure()
1136 else if (bmp_version_minor < 0x10) in parse_bmp_structure()
1138 else if (bmp_version_minor == 0x10) in parse_bmp_structure()
1140 else if (bmp_version_minor < 0x14) in parse_bmp_structure()
1142 else if (bmp_version_minor < 0x24) in parse_bmp_structure()
1145 * certainly exist by 0x24 though. in parse_bmp_structure()
1149 else if (bmp_version_minor < 0x27) in parse_bmp_structure()
1176 if (bmp_version_major < 5 || bmp_version_minor < 0x10) in parse_bmp_structure()
1190 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ in parse_bmp_structure()
1222 #if 0 in parse_bmp_structure()
1230 return 0; in parse_bmp_structure()
1237 for (i = 0; i <= (n - len); i++) { in findstr()
1238 for (j = 0; j < len; j++) in findstr()
1245 return 0; in findstr()
1255 dcb = ROMPTR(dev, drm->vbios.data[0x36]); in olddcb_table()
1261 if (dcb[0] >= 0x42) { in olddcb_table()
1262 NV_WARN(drm, "DCB version 0x%02x unknown\n", dcb[0]); in olddcb_table()
1265 if (dcb[0] >= 0x30) { in olddcb_table()
1266 if (ROM32(dcb[6]) == 0x4edcbdcb) in olddcb_table()
1269 if (dcb[0] >= 0x20) { in olddcb_table()
1270 if (ROM32(dcb[4]) == 0x4edcbdcb) in olddcb_table()
1273 if (dcb[0] >= 0x15) { in olddcb_table()
1306 if (dcb && dcb[0] >= 0x30) { in olddcb_outp()
1310 if (dcb && dcb[0] >= 0x20) { in olddcb_outp()
1316 if (dcb && dcb[0] >= 0x15) { in olddcb_outp()
1333 if (ROM32(outp[0]) == 0x00000000) in olddcb_outp_foreach()
1335 if (ROM32(outp[0]) == 0xffffffff) in olddcb_outp_foreach()
1336 break; /* seen on an NV17 with DCB v2.0 */ in olddcb_outp_foreach()
1338 if ((outp[0] & 0x0f) == DCB_OUTPUT_UNUSED) in olddcb_outp_foreach()
1340 if ((outp[0] & 0x0f) == DCB_OUTPUT_EOL) in olddcb_outp_foreach()
1348 return 0; in olddcb_outp_foreach()
1355 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) { in olddcb_conntab()
1356 u8 *conntab = ROMPTR(dev, dcb[0x14]); in olddcb_conntab()
1357 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40) in olddcb_conntab()
1376 memset(entry, 0, sizeof(struct dcb_output)); in new_dcb_entry()
1400 int link = 0; in parse_dcb20_entry()
1402 entry->type = conn & 0xf; in parse_dcb20_entry()
1403 entry->i2c_index = (conn >> 4) & 0xf; in parse_dcb20_entry()
1404 entry->heads = (conn >> 8) & 0xf; in parse_dcb20_entry()
1405 entry->connector = (conn >> 12) & 0xf; in parse_dcb20_entry()
1406 entry->bus = (conn >> 16) & 0xf; in parse_dcb20_entry()
1407 entry->location = (conn >> 20) & 0x3; in parse_dcb20_entry()
1408 entry->or = (conn >> 24) & 0xf; in parse_dcb20_entry()
1416 entry->crtconf.maxfreq = (dcb->version < 0x30) ? in parse_dcb20_entry()
1417 (conf & 0xffff) * 10 : in parse_dcb20_entry()
1418 (conf & 0xff) * 10000; in parse_dcb20_entry()
1423 if (conf & 0x1) in parse_dcb20_entry()
1425 if (dcb->version < 0x22) { in parse_dcb20_entry()
1426 mask = ~0xd; in parse_dcb20_entry()
1434 * Both 0x4 and 0x8 show up in v2.0 tables; assume they in parse_dcb20_entry()
1437 if (conf & 0x4 || conf & 0x8) in parse_dcb20_entry()
1440 mask = ~0x7; in parse_dcb20_entry()
1441 if (conf & 0x2) in parse_dcb20_entry()
1443 if (conf & 0x4) in parse_dcb20_entry()
1445 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1453 if (dcb->version >= 0x40) in parse_dcb20_entry()
1463 if (dcb->version >= 0x30) in parse_dcb20_entry()
1464 entry->tvconf.has_component_output = conf & (0x8 << 4); in parse_dcb20_entry()
1471 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1472 entry->extdev = (conf & 0x0000ff00) >> 8; in parse_dcb20_entry()
1473 switch ((conf & 0x00e00000) >> 21) { in parse_dcb20_entry()
1474 case 0: in parse_dcb20_entry()
1488 switch ((conf & 0x0f000000) >> 24) { in parse_dcb20_entry()
1489 case 0xf: in parse_dcb20_entry()
1490 case 0x4: in parse_dcb20_entry()
1493 case 0x3: in parse_dcb20_entry()
1494 case 0x2: in parse_dcb20_entry()
1504 if (dcb->version >= 0x40) { in parse_dcb20_entry()
1505 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1506 entry->extdev = (conf & 0x0000ff00) >> 8; in parse_dcb20_entry()
1509 else if (dcb->version >= 0x30) in parse_dcb20_entry()
1510 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; in parse_dcb20_entry()
1511 else if (dcb->version >= 0x22) in parse_dcb20_entry()
1512 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; in parse_dcb20_entry()
1522 if (dcb->version < 0x40) { in parse_dcb20_entry()
1533 if (conf & 0x100000) in parse_dcb20_entry()
1548 switch (conn & 0x0000000f) { in parse_dcb15_entry()
1549 case 0: in parse_dcb15_entry()
1557 if (conn & 0x10) in parse_dcb15_entry()
1566 NV_ERROR(drm, "Unknown DCB type %d\n", conn & 0x0000000f); in parse_dcb15_entry()
1570 entry->i2c_index = (conn & 0x0003c000) >> 14; in parse_dcb15_entry()
1571 entry->heads = ((conn & 0x001c0000) >> 18) + 1; in parse_dcb15_entry()
1573 entry->location = (conn & 0x01e00000) >> 21; in parse_dcb15_entry()
1574 entry->bus = (conn & 0x0e000000) >> 25; in parse_dcb15_entry()
1579 entry->crtconf.maxfreq = (conf & 0xffff) * 10; in parse_dcb15_entry()
1585 if ((conn & 0x00003f00) >> 8 != 0x10) in parse_dcb15_entry()
1600 * DCB v2.0 lists each output combination separately. in merge_like_dcb_entries()
1606 int i, newentries = 0; in merge_like_dcb_entries()
1608 for (i = 0; i < dcb->entries; i++) { in merge_like_dcb_entries()
1632 for (i = 0; i < dcb->entries; i++) { in merge_like_dcb_entries()
1664 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) { in apply_dcb_encoder_quirks()
1665 if (*conn == 0x02026312 && *conf == 0x00000020) in apply_dcb_encoder_quirks()
1674 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) { in apply_dcb_encoder_quirks()
1675 if (*conn == 0xf2005014 && *conf == 0xffffffff) { in apply_dcb_encoder_quirks()
1685 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) { in apply_dcb_encoder_quirks()
1686 if (idx == 0) { in apply_dcb_encoder_quirks()
1687 *conn = 0x02001300; /* VGA, connector 1 */ in apply_dcb_encoder_quirks()
1688 *conf = 0x00000028; in apply_dcb_encoder_quirks()
1691 *conn = 0x01010312; /* DVI, connector 0 */ in apply_dcb_encoder_quirks()
1692 *conf = 0x00020030; in apply_dcb_encoder_quirks()
1695 *conn = 0x01010310; /* VGA, connector 0 */ in apply_dcb_encoder_quirks()
1696 *conf = 0x00000028; in apply_dcb_encoder_quirks()
1699 *conn = 0x02022362; /* HDMI, connector 2 */ in apply_dcb_encoder_quirks()
1700 *conf = 0x00020010; in apply_dcb_encoder_quirks()
1702 *conn = 0x0000000e; /* EOL */ in apply_dcb_encoder_quirks()
1703 *conf = 0x00000000; in apply_dcb_encoder_quirks()
1716 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) { in apply_dcb_encoder_quirks()
1717 if (idx == 0) { in apply_dcb_encoder_quirks()
1718 *conn = 0x02002300; /* VGA, connector 2 */ in apply_dcb_encoder_quirks()
1719 *conf = 0x00000028; in apply_dcb_encoder_quirks()
1722 *conn = 0x01010312; /* DVI, connector 0 */ in apply_dcb_encoder_quirks()
1723 *conf = 0x00020030; in apply_dcb_encoder_quirks()
1726 *conn = 0x04020310; /* VGA, connector 0 */ in apply_dcb_encoder_quirks()
1727 *conf = 0x00000028; in apply_dcb_encoder_quirks()
1730 *conn = 0x02021322; /* HDMI, connector 1 */ in apply_dcb_encoder_quirks()
1731 *conf = 0x00020010; in apply_dcb_encoder_quirks()
1733 *conn = 0x0000000e; /* EOL */ in apply_dcb_encoder_quirks()
1734 *conf = 0x00000000; in apply_dcb_encoder_quirks()
1739 if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) { in apply_dcb_encoder_quirks()
1740 if (idx == 0 && *conn == 0x02000300) in apply_dcb_encoder_quirks()
1741 *conn = 0x02011300; in apply_dcb_encoder_quirks()
1743 if (idx == 1 && *conn == 0x04011310) in apply_dcb_encoder_quirks()
1744 *conn = 0x04000310; in apply_dcb_encoder_quirks()
1746 if (idx == 2 && *conn == 0x02011312) in apply_dcb_encoder_quirks()
1747 *conn = 0x02000312; in apply_dcb_encoder_quirks()
1762 fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS, 0, all_heads, DCB_OUTPUT_B); in fabricate_dcb_encoder_table()
1772 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) in fabricate_dcb_encoder_table()
1789 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); in parse_dcb_entry()
1790 u32 conn = ROM32(outp[0]); in parse_dcb_entry()
1798 if (dcb->version >= 0x20) in parse_dcb_entry()
1813 entry->i2c_index = 0x0f; in parse_dcb_entry()
1816 return 0; in parse_dcb_entry()
1824 int i, idx = 0; in dcb_fake_connectors()
1831 if (!nv_match_device(bios->dev, 0x0392, 0x107d, 0x20a2)) { in dcb_fake_connectors()
1832 for (i = 0; i < dcbt->entries; i++) { in dcb_fake_connectors()
1844 for (i = 0; i < dcbt->entries; i++) { in dcb_fake_connectors()
1846 if (i2c == 0x0f) { in dcb_fake_connectors()
1861 conntab[0] = 0x00; in dcb_fake_connectors()
1878 return 0; in parse_dcb_table()
1884 NV_INFO(drm, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf); in parse_dcb_table()
1886 dcb->version = dcbt[0]; in parse_dcb_table()
1893 if (dcb->version < 0x21) in parse_dcb_table()
1899 if (conn[0] != 0xff) { in parse_dcb_table()
1902 idx, ROM16(conn[0])); in parse_dcb_table()
1905 idx, ROM32(conn[0])); in parse_dcb_table()
1909 return 0; in parse_dcb_table()
1919 * (0x00001304), followed by the ucode bytes, written sequentially, in load_nv17_hwsq_ucode_entry()
1920 * starting at reg 0x00001400 in load_nv17_hwsq_ucode_entry()
1947 nvif_wr32(device, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); in load_nv17_hwsq_ucode_entry()
1951 for (i = 0; i < bytes_to_write; i += 4) in load_nv17_hwsq_ucode_entry()
1952 nvif_wr32(device, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); in load_nv17_hwsq_ucode_entry()
1955 nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); in load_nv17_hwsq_ucode_entry()
1957 return 0; in load_nv17_hwsq_ucode_entry()
1978 return 0; in load_nv17_hw_sequencer_ucode()
1980 /* always use entry 0? */ in load_nv17_hw_sequencer_ucode()
1981 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); in load_nv17_hw_sequencer_ucode()
1989 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; in nouveau_bios_embedded_edid()
1990 uint16_t offset = 0; in nouveau_bios_embedded_edid()
2021 memset(legacy, 0, sizeof(struct nvbios)); in NVInitVBIOS()
2049 /* Reset the BIOS head to 0. */ in nouveau_run_vbios_init()
2050 bios->state.crtchead = 0; in nouveau_run_vbios_init()
2056 bios->fp.last_script_invoc = 0; in nouveau_run_vbios_init()
2060 return 0; in nouveau_run_vbios_init()
2072 htotal = NVReadVgaCrtc(dev, 0, 0x06); in nouveau_bios_posted()
2073 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; in nouveau_bios_posted()
2074 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; in nouveau_bios_posted()
2075 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; in nouveau_bios_posted()
2076 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; in nouveau_bios_posted()
2077 return (htotal != 0); in nouveau_bios_posted()
2090 return 0; in nouveau_bios_init()
2101 if (!bios->major_version) /* we don't run version 0 bios */ in nouveau_bios_init()
2102 return 0; in nouveau_bios_init()
2120 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; in nouveau_bios_init()
2129 return 0; in nouveau_bios_init()