54 	uint32_t sample = 0;  in nv42_tv_sample_load()
57 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)  in nv42_tv_sample_load()
58 	testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);  in nv42_tv_sample_load()
62 	dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);  in nv42_tv_sample_load()
63 	head = (dacclk & 0x100) >> 8;  in nv42_tv_sample_load()
66 	gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);  in nv42_tv_sample_load()
67 	gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);  in nv42_tv_sample_load()
72 	test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);  in nv42_tv_sample_load()
73 	ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);  in nv42_tv_sample_load()
74 	ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);  in nv42_tv_sample_load()
75 	ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);  in nv42_tv_sample_load()
78 	nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);  in nv42_tv_sample_load()
79 	nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);  in nv42_tv_sample_load()
91 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);  in nv42_tv_sample_load()
93 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,  in nv42_tv_sample_load()
94 		      (dacclk & ~0xff) | 0x22);  in nv42_tv_sample_load()
96 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,  in nv42_tv_sample_load()
97 		      (dacclk & ~0xff) | 0x21);  in nv42_tv_sample_load()
99 	NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);  in nv42_tv_sample_load()
100 	NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);  in nv42_tv_sample_load()
102 	/* Sample pin 0x4 (usually S-video luma). */  in nv42_tv_sample_load()
103 	NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);  in nv42_tv_sample_load()
105 	sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)  in nv42_tv_sample_load()
106 		& 0x4 << 28;  in nv42_tv_sample_load()
109 	NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);  in nv42_tv_sample_load()
111 	sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)  in nv42_tv_sample_load()
112 		& 0xa << 28;  in nv42_tv_sample_load()
115 	NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);  in nv42_tv_sample_load()
116 	NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);  in nv42_tv_sample_load()
117 	NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);  in nv42_tv_sample_load()
118 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);  in nv42_tv_sample_load()
119 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);  in nv42_tv_sample_load()
124 	nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);  in nv42_tv_sample_load()
125 	nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);  in nv42_tv_sample_load()
158 		if (drm->client.device.info.chipset == 0x42 ||  in nv17_tv_detect()
159 		    drm->client.device.info.chipset == 0x43)  in nv17_tv_detect()
161 				nv42_tv_sample_load(encoder) >> 28 & 0xe;  in nv17_tv_detect()
164 				nv17_dac_sample_load(encoder) >> 28 & 0xe;  in nv17_tv_detect()
168 	case 0x2:  in nv17_tv_detect()
169 	case 0x4:  in nv17_tv_detect()
172 	case 0xc:  in nv17_tv_detect()
175 	case 0xe:  in nv17_tv_detect()
206 	int n = 0;  in nv17_tv_get_ld_modes()
253 	int i, n = 0;  in nv17_tv_get_hd_modes()
255 	for (i = 0; i < ARRAY_SIZE(modes); i++) {  in nv17_tv_get_hd_modes()
397 	nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);  in nv17_tv_dpms()
398 	nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);  in nv17_tv_dpms()
440 		*cr_lcd |= 0x1 | (head ? 0x0 : 0x8);  in nv17_tv_prepare()
443 	dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;  in nv17_tv_prepare()
446 		dacclk |= 0x1a << 16;  in nv17_tv_prepare()
449 		dacclk |=  0x20;  in nv17_tv_prepare()
452 			dacclk |= 0x100;  in nv17_tv_prepare()
454 			dacclk &= ~0x100;  in nv17_tv_prepare()
457 		dacclk |= 0x10;  in nv17_tv_prepare()
461 	NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);  in nv17_tv_prepare()
476 	regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */  in nv17_tv_mode_set()
477 	regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */  in nv17_tv_mode_set()
478 	regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */  in nv17_tv_mode_set()
480 	regs->ramdac_8c0 = 0x0;  in nv17_tv_mode_set()
483 		tv_regs->ptv_200 = 0x13111100;  in nv17_tv_mode_set()
485 			tv_regs->ptv_200 |= 0x10;  in nv17_tv_mode_set()
487 		tv_regs->ptv_20c = 0x808010;  in nv17_tv_mode_set()
488 		tv_regs->ptv_304 = 0x2d00000;  in nv17_tv_mode_set()
489 		tv_regs->ptv_600 = 0x0;  in nv17_tv_mode_set()
490 		tv_regs->ptv_60c = 0x0;  in nv17_tv_mode_set()
491 		tv_regs->ptv_610 = 0x1e00000;  in nv17_tv_mode_set()
494 			tv_regs->ptv_508 = 0x1200000;  in nv17_tv_mode_set()
495 			tv_regs->ptv_614 = 0x33;  in nv17_tv_mode_set()
498 			tv_regs->ptv_508 = 0xf00000;  in nv17_tv_mode_set()
499 			tv_regs->ptv_614 = 0x13;  in nv17_tv_mode_set()
503 			tv_regs->ptv_500 = 0xe8e0;  in nv17_tv_mode_set()
504 			tv_regs->ptv_504 = 0x1710;  in nv17_tv_mode_set()
505 			tv_regs->ptv_604 = 0x0;  in nv17_tv_mode_set()
506 			tv_regs->ptv_608 = 0x0;  in nv17_tv_mode_set()
509 				tv_regs->ptv_604 = 0x20;  in nv17_tv_mode_set()
510 				tv_regs->ptv_608 = 0x10;  in nv17_tv_mode_set()
511 				tv_regs->ptv_500 = 0x19710;  in nv17_tv_mode_set()
512 				tv_regs->ptv_504 = 0x68f0;  in nv17_tv_mode_set()
515 				tv_regs->ptv_604 = 0x10;  in nv17_tv_mode_set()
516 				tv_regs->ptv_608 = 0x20;  in nv17_tv_mode_set()
517 				tv_regs->ptv_500 = 0x4b90;  in nv17_tv_mode_set()
518 				tv_regs->ptv_504 = 0x1b480;  in nv17_tv_mode_set()
522 		for (i = 0; i < 0x40; i++)  in nv17_tv_mode_set()
529 		/* The registers in PRAMDAC+0xc00 control some timings and CSC  in nv17_tv_mode_set()
537 		for (i = 0; i < 38; i++)  in nv17_tv_mode_set()
572 		regs->fp_debug_2 = 0;  in nv17_tv_mode_set()
574 		regs->fp_margin_color = 0x801080;  in nv17_tv_mode_set()
597 	if (drm->client.device.info.chipset < 0x44)  in nv17_tv_commit()
598 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +  in nv17_tv_commit()
600 					0xf0000000);  in nv17_tv_commit()
602 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +  in nv17_tv_commit()
604 					0x00100000);  in nv17_tv_commit()
619 					NVReadRAMDAC(dev, 0,  in nv17_tv_save()
632 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +  in nv17_tv_restore()
656 		if (i < 0)  in nv17_tv_create_resources()
687 	return 0;  in nv17_tv_create_resources()
752 		drm_helper_probe_single_connector_modes(connector, 0, 0);  in nv17_tv_set_property()
762 	return 0;  in nv17_tv_set_property()
807 	tv_enc->hue = 0;  in nv17_tv_create()
811 	tv_enc->pin_mask = 0;  in nv17_tv_create()
827 	encoder->possible_clones = 0;  in nv17_tv_create()
831 	return 0;  in nv17_tv_create()