Lines Matching +full:0 +full:x00001000
29 #define NV_PMC_OFFSET 0x00000000
30 #define NV_PMC_SIZE 0x00001000
32 #define NV_PBUS_OFFSET 0x00001000
33 #define NV_PBUS_SIZE 0x00001000
35 #define NV_PFIFO_OFFSET 0x00002000
36 #define NV_PFIFO_SIZE 0x00002000
38 #define NV_HDIAG_OFFSET 0x00005000
39 #define NV_HDIAG_SIZE 0x00001000
41 #define NV_PRAM_OFFSET 0x00006000
42 #define NV_PRAM_SIZE 0x00001000
44 #define NV_PVIDEO_OFFSET 0x00008000
45 #define NV_PVIDEO_SIZE 0x00001000
47 #define NV_PTIMER_OFFSET 0x00009000
48 #define NV_PTIMER_SIZE 0x00001000
50 #define NV_PPM_OFFSET 0x0000A000
51 #define NV_PPM_SIZE 0x00001000
53 #define NV_PTV_OFFSET 0x0000D000
54 #define NV_PTV_SIZE 0x00001000
56 #define NV_PRMVGA_OFFSET 0x000A0000
57 #define NV_PRMVGA_SIZE 0x00020000
59 #define NV_PRMVIO0_OFFSET 0x000C0000
60 #define NV_PRMVIO_SIZE 0x00002000
61 #define NV_PRMVIO1_OFFSET 0x000C2000
63 #define NV_PFB_OFFSET 0x00100000
64 #define NV_PFB_SIZE 0x00001000
66 #define NV_PEXTDEV_OFFSET 0x00101000
67 #define NV_PEXTDEV_SIZE 0x00001000
69 #define NV_PME_OFFSET 0x00200000
70 #define NV_PME_SIZE 0x00001000
72 #define NV_PROM_OFFSET 0x00300000
73 #define NV_PROM_SIZE 0x00010000
75 #define NV_PGRAPH_OFFSET 0x00400000
76 #define NV_PGRAPH_SIZE 0x00010000
78 #define NV_PCRTC0_OFFSET 0x00600000
79 #define NV_PCRTC0_SIZE 0x00002000 /* empirical */
81 #define NV_PRMCIO0_OFFSET 0x00601000
82 #define NV_PRMCIO_SIZE 0x00002000
83 #define NV_PRMCIO1_OFFSET 0x00603000
85 #define NV50_DISPLAY_OFFSET 0x00610000
86 #define NV50_DISPLAY_SIZE 0x0000FFFF
88 #define NV_PRAMDAC0_OFFSET 0x00680000
89 #define NV_PRAMDAC0_SIZE 0x00002000
91 #define NV_PRMDIO0_OFFSET 0x00681000
92 #define NV_PRMDIO_SIZE 0x00002000
93 #define NV_PRMDIO1_OFFSET 0x00683000
95 #define NV_PRAMIN_OFFSET 0x00700000
96 #define NV_PRAMIN_SIZE 0x00100000
98 #define NV_FIFO_OFFSET 0x00800000
99 #define NV_FIFO_SIZE 0x00800000
101 #define NV_PMC_BOOT_0 0x00000000
102 #define NV_PMC_ENABLE 0x00000200
104 #define NV_VIO_VSE2 0x000003c3
105 #define NV_VIO_SRX 0x000003c4
107 #define NV_CIO_CRX__COLOR 0x000003d4
108 #define NV_CIO_CR__COLOR 0x000003d5
110 #define NV_PBUS_DEBUG_1 0x00001084
111 #define NV_PBUS_DEBUG_4 0x00001098
112 #define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0
113 #define NV_PBUS_POWERCTRL_1 0x00001584
114 #define NV_PBUS_POWERCTRL_2 0x00001588
115 #define NV_PBUS_POWERCTRL_4 0x00001590
116 #define NV_PBUS_PCI_NV_19 0x0000184C
117 #define NV_PBUS_PCI_NV_20 0x00001850
118 # define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0)
119 # define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0)
121 #define NV_PFIFO_RAMHT 0x00002210
123 #define NV_PTV_TV_INDEX 0x0000d220
124 #define NV_PTV_TV_DATA 0x0000d224
125 #define NV_PTV_HFILTER 0x0000d310
126 #define NV_PTV_HFILTER2 0x0000d390
127 #define NV_PTV_VFILTER 0x0000d510
129 #define NV_PRMVIO_MISC__WRITE 0x000c03c2
130 #define NV_PRMVIO_SRX 0x000c03c4
131 #define NV_PRMVIO_SR 0x000c03c5
132 # define NV_VIO_SR_RESET_INDEX 0x00
133 # define NV_VIO_SR_CLOCK_INDEX 0x01
134 # define NV_VIO_SR_PLANE_MASK_INDEX 0x02
135 # define NV_VIO_SR_CHAR_MAP_INDEX 0x03
136 # define NV_VIO_SR_MEM_MODE_INDEX 0x04
137 #define NV_PRMVIO_MISC__READ 0x000c03cc
138 #define NV_PRMVIO_GRX 0x000c03ce
139 #define NV_PRMVIO_GX 0x000c03cf
140 # define NV_VIO_GX_SR_INDEX 0x00
141 # define NV_VIO_GX_SREN_INDEX 0x01
142 # define NV_VIO_GX_CCOMP_INDEX 0x02
143 # define NV_VIO_GX_ROP_INDEX 0x03
144 # define NV_VIO_GX_READ_MAP_INDEX 0x04
145 # define NV_VIO_GX_MODE_INDEX 0x05
146 # define NV_VIO_GX_MISC_INDEX 0x06
147 # define NV_VIO_GX_DONT_CARE_INDEX 0x07
148 # define NV_VIO_GX_BIT_MASK_INDEX 0x08
150 #define NV_PCRTC_INTR_0 0x00600100
151 # define NV_PCRTC_INTR_0_VBLANK (1 << 0)
152 #define NV_PCRTC_INTR_EN_0 0x00600140
153 #define NV_PCRTC_START 0x00600800
154 #define NV_PCRTC_CONFIG 0x00600804
155 # define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA (1 << 0)
156 # define NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC (4 << 0)
157 # define NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC (2 << 0)
158 #define NV_PCRTC_CURSOR_CONFIG 0x00600810
159 # define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE (1 << 0)
168 /* note: PCRTC_GPIO is not available on nv10, and in fact aliases 0x600810 */
169 #define NV_PCRTC_GPIO 0x00600818
170 #define NV_PCRTC_GPIO_EXT 0x0060081c
171 #define NV_PCRTC_830 0x00600830
172 #define NV_PCRTC_834 0x00600834
173 #define NV_PCRTC_850 0x00600850
174 #define NV_PCRTC_ENGINE_CTRL 0x00600860
178 #define NV_PRMCIO_ARX 0x006013c0
179 #define NV_PRMCIO_AR__WRITE 0x006013c0
180 #define NV_PRMCIO_AR__READ 0x006013c1
181 # define NV_CIO_AR_MODE_INDEX 0x10
182 # define NV_CIO_AR_OSCAN_INDEX 0x11
183 # define NV_CIO_AR_PLANE_INDEX 0x12
184 # define NV_CIO_AR_HPP_INDEX 0x13
185 # define NV_CIO_AR_CSEL_INDEX 0x14
186 #define NV_PRMCIO_INP0 0x006013c2
187 #define NV_PRMCIO_CRX__COLOR 0x006013d4
188 #define NV_PRMCIO_CR__COLOR 0x006013d5
190 # define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */
191 # define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */
192 # define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */
193 # define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */
194 # define NV_CIO_CR_HBE_4_0 4:0
195 # define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */
196 # define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */
197 # define NV_CIO_CR_HRE_4_0 4:0
199 # define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */
200 # define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */
201 # define NV_CIO_CR_OVL_VDT_8 0:0
208 # define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */
209 # define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */
212 # define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */
213 # define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */
214 # define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */
215 # define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */
216 # define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */
217 # define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */
218 # define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */
219 # define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */
220 # define NV_CIO_CR_VRE_3_0 3:0
221 # define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */
222 # define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */
223 # define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */
224 # define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */
225 # define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */
226 # define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */
227 # define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */
229 # define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */
231 # define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */
233 # define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */
234 # define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */
235 # define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */
236 # define NV_CIO_SR_UNLOCK_RW_VALUE 0x57
237 # define NV_CIO_SR_LOCK_VALUE 0x99
238 # define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */
239 # define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */
240 # define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */
241 # define NV_CIO_CRE_LSR_VDT_10 0:0
246 # define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */
247 # define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */
248 # define NV_CIO_CRE_PIXEL_INDEX 0x28
249 # define NV_CIO_CRE_PIXEL_FORMAT 1:0
250 # define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */
251 # define NV_CIO_CRE_HEB_HDT_8 0:0
256 # define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */
257 # define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */
258 # define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */
259 # define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0
261 # define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */
262 # define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0
265 # define NV_CIO_CRE_LCD__INDEX 0x33
266 # define NV_CIO_CRE_LCD_LCD_SELECT 0:0
267 # define NV_CIO_CRE_LCD_ROUTE_MASK 0x3b
268 # define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36
269 # define NV_CIO_CRE_DDC0_WR__INDEX 0x37
270 # define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */
271 # define NV_CIO_CRE_SCRATCH3__INDEX 0x3b
272 # define NV_CIO_CRE_SCRATCH4__INDEX 0x3c
273 # define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e
274 # define NV_CIO_CRE_DDC_WR__INDEX 0x3f
275 # define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */
276 # define NV_CIO_CRE_EBR_VDT_11 0:0
280 # define NV_CIO_CRE_42 0x42
282 # define NV_CIO_CRE_43 0x43
283 # define NV_CIO_CRE_44 0x44 /* head control */
284 # define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */
285 # define NV_CIO_CRE_RCR 0x46
287 # define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */
288 # define NV_CIO_CRE_49 0x49
289 # define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */
290 # define NV_CIO_CRE_TVOUT_LATENCY 0x52
291 # define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */
292 # define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */
293 # define NV_CIO_CRE_57 0x57 /* index reg for cr58 */
294 # define NV_CIO_CRE_58 0x58 /* data reg for cr57 */
295 # define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */
296 # define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */
297 # define NV_CIO_CRE_85 0x85
298 # define NV_CIO_CRE_86 0x86
299 #define NV_PRMCIO_INP0__COLOR 0x006013da
301 #define NV_PRAMDAC_CU_START_POS 0x00680300
302 # define NV_PRAMDAC_CU_START_POS_X 15:0
304 #define NV_RAMDAC_NV10_CURSYNC 0x00680404
306 #define NV_PRAMDAC_NVPLL_COEFF 0x00680500
307 #define NV_PRAMDAC_MPLL_COEFF 0x00680504
308 #define NV_PRAMDAC_VPLL_COEFF 0x00680508
311 #define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050c
312 # define NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE (4 << 0)
325 #define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510
326 #define NV_RAMDAC_VPLL2 0x00680520
327 #define NV_PRAMDAC_SEL_CLK 0x00680524
328 #define NV_RAMDAC_DITHER_NV11 0x00680528
329 #define NV_PRAMDAC_DACCLK 0x0068052c
330 # define NV_PRAMDAC_DACCLK_SEL_DACCLK (1 << 0)
332 #define NV_RAMDAC_NVPLL_B 0x00680570
333 #define NV_RAMDAC_MPLL_B 0x00680574
334 #define NV_RAMDAC_VPLL_B 0x00680578
335 #define NV_RAMDAC_VPLL2_B 0x0068057c
337 #define NV_PRAMDAC_580 0x00680580
341 #define NV_PRAMDAC_GENERAL_CONTROL 0x00680600
348 #define NV_PRAMDAC_TEST_CONTROL 0x00680608
352 #define NV_PRAMDAC_TESTPOINT_DATA 0x00680610
354 #define NV_PRAMDAC_630 0x00680630
355 #define NV_PRAMDAC_634 0x00680634
357 #define NV_PRAMDAC_TV_SETUP 0x00680700
358 #define NV_PRAMDAC_TV_VTOTAL 0x00680720
359 #define NV_PRAMDAC_TV_VSKEW 0x00680724
360 #define NV_PRAMDAC_TV_VSYNC_DELAY 0x00680728
361 #define NV_PRAMDAC_TV_HTOTAL 0x0068072c
362 #define NV_PRAMDAC_TV_HSKEW 0x00680730
363 #define NV_PRAMDAC_TV_HSYNC_DELAY 0x00680734
364 #define NV_PRAMDAC_TV_HSYNC_DELAY2 0x00680738
366 #define NV_PRAMDAC_TV_SETUP 0x00680700
368 #define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800
369 #define NV_PRAMDAC_FP_VTOTAL 0x00680804
370 #define NV_PRAMDAC_FP_VCRTC 0x00680808
371 #define NV_PRAMDAC_FP_VSYNC_START 0x0068080c
372 #define NV_PRAMDAC_FP_VSYNC_END 0x00680810
373 #define NV_PRAMDAC_FP_VVALID_START 0x00680814
374 #define NV_PRAMDAC_FP_VVALID_END 0x00680818
375 #define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820
376 #define NV_PRAMDAC_FP_HTOTAL 0x00680824
377 #define NV_PRAMDAC_FP_HCRTC 0x00680828
378 #define NV_PRAMDAC_FP_HSYNC_START 0x0068082c
379 #define NV_PRAMDAC_FP_HSYNC_END 0x00680830
380 #define NV_PRAMDAC_FP_HVALID_START 0x00680834
381 #define NV_PRAMDAC_FP_HVALID_END 0x00680838
383 #define NV_RAMDAC_FP_DITHER 0x0068083c
384 #define NV_PRAMDAC_FP_TG_CONTROL 0x00680848
385 # define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS (1 << 0)
386 # define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE (2 << 0)
389 # define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE (0 << 8)
396 #define NV_PRAMDAC_FP_MARGIN_COLOR 0x0068084c
397 #define NV_PRAMDAC_850 0x00680850
398 #define NV_PRAMDAC_85C 0x0068085c
399 #define NV_PRAMDAC_FP_DEBUG_0 0x00680880
400 # define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE (1 << 0)
409 #define NV_PRAMDAC_FP_DEBUG_1 0x00680884
410 # define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0
414 #define NV_PRAMDAC_FP_DEBUG_2 0x00680888
415 #define NV_PRAMDAC_FP_DEBUG_3 0x0068088C
418 #define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808b0
420 #define NV_PRAMDAC_FP_TMDS_DATA 0x006808b4
422 #define NV_PRAMDAC_8C0 0x006808c0
425 #define NV_PRAMDAC_900 0x00680900
426 #define NV_PRAMDAC_A20 0x00680A20
427 #define NV_PRAMDAC_A24 0x00680A24
428 #define NV_PRAMDAC_A34 0x00680A34
430 #define NV_PRAMDAC_CTV 0x00680c00
433 #define NV_PRMDIO_PIXEL_MASK 0x006813c6
434 # define NV_PRMDIO_PIXEL_MASK_MASK 0xff
435 #define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7
436 #define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8
437 #define NV_PRMDIO_PALETTE_DATA 0x006813c9
439 #define NV_PGRAPH_DEBUG_0 0x00400080
440 #define NV_PGRAPH_DEBUG_1 0x00400084
441 #define NV_PGRAPH_DEBUG_2_NV04 0x00400088
442 #define NV_PGRAPH_DEBUG_2 0x00400620
443 #define NV_PGRAPH_DEBUG_3 0x0040008c
444 #define NV_PGRAPH_DEBUG_4 0x00400090
445 #define NV_PGRAPH_INTR 0x00400100
446 #define NV_PGRAPH_INTR_EN 0x00400140
447 #define NV_PGRAPH_CTX_CONTROL 0x00400144
448 #define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170
449 #define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
450 #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
451 #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
452 #define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
453 #define NV_PGRAPH_BETA_AND 0x00400608
454 #define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610
455 #define NV_PGRAPH_BOFFSET0 0x00400640
456 #define NV_PGRAPH_BOFFSET1 0x00400644
457 #define NV_PGRAPH_BOFFSET2 0x00400648
458 #define NV_PGRAPH_BLIMIT0 0x00400684
459 #define NV_PGRAPH_BLIMIT1 0x00400688
460 #define NV_PGRAPH_BLIMIT2 0x0040068c
461 #define NV_PGRAPH_STATUS 0x00400700
462 #define NV_PGRAPH_SURFACE 0x00400710
463 #define NV_PGRAPH_STATE 0x00400714
464 #define NV_PGRAPH_FIFO 0x00400720
465 #define NV_PGRAPH_PATTERN_SHAPE 0x00400810
466 #define NV_PGRAPH_TILE 0x00400b00
468 #define NV_PVIDEO_INTR_EN 0x00008140
469 #define NV_PVIDEO_BUFFER 0x00008700
470 #define NV_PVIDEO_STOP 0x00008704
471 #define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4)
472 #define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4)
473 #define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4)
474 #define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4)
475 #define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4)
476 #define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4)
477 #define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4)
478 #define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4)
479 #define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4)
480 #define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4)
481 #define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4)
482 #define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4)
483 #define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4)
484 #define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4)
485 #define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4)
486 # define NV_PVIDEO_FORMAT_PLANAR (1 << 0)
490 #define NV_PVIDEO_COLOR_KEY 0x00008B00
493 #define NV_PVIDEO_INTR_EN_0 0x00680140
494 #define NV_PVIDEO_STEP_SIZE 0x00680200
495 #define NV_PVIDEO_CONTROL_Y 0x00680204
496 #define NV_PVIDEO_CONTROL_X 0x00680208
497 #define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c
498 #define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214
499 #define NV_PVIDEO_BUFF0_OFFSET 0x0068021c
500 #define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210
501 #define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218
502 #define NV_PVIDEO_BUFF1_OFFSET 0x00680220
503 #define NV_PVIDEO_OE_STATE 0x00680224
504 #define NV_PVIDEO_SU_STATE 0x00680228
505 #define NV_PVIDEO_RM_STATE 0x0068022c
506 #define NV_PVIDEO_WINDOW_START 0x00680230
507 #define NV_PVIDEO_WINDOW_SIZE 0x00680234
508 #define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238
509 #define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c
510 #define NV_PVIDEO_KEY 0x00680240
511 #define NV_PVIDEO_OVERLAY 0x00680244
512 #define NV_PVIDEO_RED_CSC_OFFSET 0x00680280
513 #define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284
514 #define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288
515 #define NV_PVIDEO_CSC_ADJUST 0x0068028c