379 rd_cio_state(struct drm_device *dev, int head,  in rd_cio_state()  function
549 		rd_cio_state(dev, head, regp, i);  in nv_save_state_vga()
597 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);  in nv_save_state_ext()
598 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);  in nv_save_state_ext()
599 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);  in nv_save_state_ext()
600 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);  in nv_save_state_ext()
601 	rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);  in nv_save_state_ext()
602 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);  in nv_save_state_ext()
603 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);  in nv_save_state_ext()
605 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);  in nv_save_state_ext()
606 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);  in nv_save_state_ext()
607 	rd_cio_state(dev, head, regp, NV_CIO_CRE_21);  in nv_save_state_ext()
610 		rd_cio_state(dev, head, regp, NV_CIO_CRE_47);  in nv_save_state_ext()
613 		rd_cio_state(dev, head, regp, 0x9f);  in nv_save_state_ext()
615 	rd_cio_state(dev, head, regp, NV_CIO_CRE_49);  in nv_save_state_ext()
616 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);  in nv_save_state_ext()
617 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);  in nv_save_state_ext()
618 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);  in nv_save_state_ext()
619 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);  in nv_save_state_ext()
638 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);  in nv_save_state_ext()
639 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);  in nv_save_state_ext()
641 		rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);  in nv_save_state_ext()
642 		rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);  in nv_save_state_ext()
643 		rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);  in nv_save_state_ext()
644 		rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);  in nv_save_state_ext()
648 		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);  in nv_save_state_ext()
649 		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);  in nv_save_state_ext()
650 		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);  in nv_save_state_ext()
654 		rd_cio_state(dev, head, regp, NV_CIO_CRE_59);  in nv_save_state_ext()
655 		rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);  in nv_save_state_ext()
657 		rd_cio_state(dev, head, regp, NV_CIO_CRE_85);  in nv_save_state_ext()
658 		rd_cio_state(dev, head, regp, NV_CIO_CRE_86);  in nv_save_state_ext()