Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define CTRL_SFTRST BIT(31)
40 #define CTRL_CLKGATE BIT(30)
41 #define CTRL_BYPASS_COUNT BIT(19)
42 #define CTRL_VSYNC_MODE BIT(18)
43 #define CTRL_DOTCLK_MODE BIT(17)
44 #define CTRL_DATA_SELECT BIT(16)
54 #define CTRL_MASTER BIT(5)
55 #define CTRL_DF16 BIT(3)
56 #define CTRL_DF18 BIT(2)
57 #define CTRL_DF24 BIT(1)
58 #define CTRL_RUN BIT(0)
60 #define CTRL1_RECOVER_ON_UNDERFLOW BIT(24)
61 #define CTRL1_FIFO_CLEAR BIT(21)
62 #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
63 #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
64 #define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13)
65 #define CTRL1_CUR_FRAME_DONE_IRQ BIT(9)
74 #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
75 #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
79 #define VDCTRL0_ENABLE_PRESENT BIT(28)
80 #define VDCTRL0_VSYNC_ACT_HIGH BIT(27)
81 #define VDCTRL0_HSYNC_ACT_HIGH BIT(26)
82 #define VDCTRL0_DOTCLK_ACT_FALLING BIT(25)
83 #define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
84 #define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
85 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20)
86 #define VDCTRL0_HALF_LINE BIT(19)
87 #define VDCTRL0_HALF_LINE_MODE BIT(18)
94 #define VDCTRL3_MUX_SYNC_SIGNALS BIT(29)
95 #define VDCTRL3_VSYNC_ONLY BIT(28)
96 #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
97 #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
103 #define VDCTRL4_SYNC_SIGNALS_ON BIT(18)
106 #define DEBUG0_HSYNC BIT(26)
107 #define DEBUG0_VSYNC BIT(25)
109 #define AS_CTRL_PS_DISABLE BIT(23)
110 #define AS_CTRL_ALPHA_INVERT BIT(20)
119 #define AS_CTRL_ENABLE_COLORKEY BIT(3)
124 #define AS_CTRL_AS_ENABLE BIT(0)
127 #define CTRL_SW_RESET BIT(31)
129 #define CTRL_FETCH_START_OPTION_PWV BIT(8)
130 #define CTRL_FETCH_START_OPTION_BPV BIT(9)
133 #define CTRL_NEG BIT(4)
134 #define CTRL_INV_PXCK BIT(3)
135 #define CTRL_INV_DE BIT(2)
136 #define CTRL_INV_VS BIT(1)
137 #define CTRL_INV_HS BIT(0)
139 #define DISP_PARA_DISP_ON BIT(31)
140 #define DISP_PARA_SWAP_EN BIT(30)
146 #define DISP_PARA_BGND_R_MASK GENMASK(23, 16)
150 #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16)
151 #define DISP_SIZE_DELTA_Y_MASK GENMASK(31, 16)
155 #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16)
156 #define HSYN_PARA_BP_H_MASK GENMASK(31, 16)
160 #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16)
161 #define VSYN_PARA_BP_V_MASK GENMASK(31, 16)
165 #define VSYN_HSYN_WIDTH_PW_V(n) (((n) & 0xffff) << 16)
166 #define VSYN_HSYN_WIDTH_PW_V_MASK GENMASK(31, 16)
170 #define INT_STATUS_D0_FIFO_EMPTY BIT(24)
171 #define INT_STATUS_D0_DMA_DONE BIT(16)
172 #define INT_STATUS_D0_DMA_ERR BIT(8)
173 #define INT_STATUS_D0_VS_BLANK BIT(2)
174 #define INT_STATUS_D0_UNDERRUN BIT(1)
175 #define INT_STATUS_D0_VSYNC BIT(0)
177 #define INT_ENABLE_D0_FIFO_EMPTY_EN BIT(24)
178 #define INT_ENABLE_D0_DMA_DONE_EN BIT(16)
179 #define INT_ENABLE_D0_DMA_ERR_EN BIT(8)
180 #define INT_ENABLE_D0_VS_BLANK_EN BIT(2)
181 #define INT_ENABLE_D0_UNDERRUN_EN BIT(1)
182 #define INT_ENABLE_D0_VSYNC_EN BIT(0)
184 #define INT_STATUS_D1_PLANE_PANIC BIT(0)
186 #define INT_ENABLE_D1_PLANE_PANIC_EN BIT(0)
188 #define CTRLDESCL0_1_HEIGHT(n) (((n) & 0xffff) << 16)
189 #define CTRLDESCL0_1_HEIGHT_MASK GENMASK(31, 16)
195 #define CTRLDESCL0_3_T_SIZE(n) (((n) << 16) & CTRLDESCL0_3_T_SIZE_MASK)
196 #define CTRLDESCL0_3_T_SIZE_MASK GENMASK(17, 16)
203 #define CTRLDESCL0_5_EN BIT(31)
204 #define CTRLDESCL0_5_SHADOW_LOAD_EN BIT(30)
224 #define CSC0_CTRL_BYPASS BIT(0)
226 #define CSC0_COEF0_A2(n) (((n) << 16) & CSC0_COEF0_A2_MASK)
227 #define CSC0_COEF0_A2_MASK GENMASK(26, 16)
231 #define CSC0_COEF1_B1(n) (((n) << 16) & CSC0_COEF1_B1_MASK)
232 #define CSC0_COEF1_B1_MASK GENMASK(26, 16)
236 #define CSC0_COEF2_B3(n) (((n) << 16) & CSC0_COEF2_B3_MASK)
237 #define CSC0_COEF2_B3_MASK GENMASK(26, 16)
241 #define CSC0_COEF3_C2(n) (((n) << 16) & CSC0_COEF3_C2_MASK)
242 #define CSC0_COEF3_C2_MASK GENMASK(26, 16)
246 #define CSC0_COEF4_D1(n) (((n) << 16) & CSC0_COEF4_D1_MASK)
247 #define CSC0_COEF4_D1_MASK GENMASK(24, 16)
251 #define CSC0_COEF5_D3(n) (((n) << 16) & CSC0_COEF5_D3_MASK)
252 #define CSC0_COEF5_D3_MASK GENMASK(24, 16)
256 #define PANIC0_THRES_LOW_MASK GENMASK(24, 16)